fix: synthesis bugs, arbitration race conditions, and scheduler logic

[ridash2005]

This PR implements critical fixes to the src directory to resolve synthesis failures, eliminate race conditions, and correct logic bugs that were preventing proper GPU instruction execution. The changes ensure the design adheres to standard SystemVerilog structural modeling rules and produces deterministic hardware.

1. Controller Arbitration Fix (
   src/controller.sv
   )
   Issue: The previous arbitration logic used blocking assignments inside a sequential loop (channel_serving_consumer[j] = 1), causing "Multiple Driver" errors during synthesis where multiple channels could try to write to the same register bit in the same cycle.
   Fix: Refactored the logic to use a combinatorial next_state variable pattern. Arbitration allows only one consumer-to-channel mapping per cycle, and the state register is updated strictly at the end of the clock edge.

2. Scheduler Stall & Logic Fixes (
   src/scheduler.sv
   )
   Critical Fix: The PC update logic previously relied on next_pc[THREADS_PER_BLOCK-1]. In blocks with fewer than maximum threads (e.g., partial blocks), the last thread is inactive, causing the core to read a zero/invalid PC. The logic now uses Thread 0 (next_pc[0]), which is guaranteed to be active for any valid block.
   Logic Fix: Fixed any_lsu_waiting being declared as a static variable inside an always block. It is now a proper temporary logic variable that resets every cycle.
   Syntax: Removed an invalid trailing comma in the parameter list.

3. Core Structural Corrections (
   src/core.sv
   )
   Issue: Internal signals driven by submodule output ports (like instruction, rs, rt) were declared as reg. This violates strict Verilog structural modeling.
   Fix: Converted all such internal signals to wire to match their structural connections.

4. Deterministic Dispatch (
   src/dispatch.sv
   )
   Fix: Replaced mixed blocking (=) and non-blocking (<=) assignments with consistent non-blocking assignments for state variables (blocks_dispatched, blocks_done) to ensure deterministic sequential behavior.

5. Syntax & Typos
   src/dcr.sv
   : Fixed variable name typo device_conrol_register → device_control_register. Removed trailing comma in port list.
   src/gpu.sv
   : Removed invalid trailing comma in core module instantiation.