Add Makefile.sv to directly simulate SV files using tools like VCS #38

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filamoon wants to merge 1 commit into adam-maj:master from filamoon:moreEDA

filamoon commented Feb 23, 2025

So no need to use other tools to first convert SV to verilog.


          Add Makefile.sv to directly simulate SV files using tools like VCS an…

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