core.Mmio: Respect field access type

core/src/cpus/cortex_m.zig

@@ -2,8 +2,6 @@ const std = @import("std");
 const builtin = @import("builtin");
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
-const app = microzig.app;
-const shared = @import("cortex_m/shared_types.zig");
 const VectorTable = microzig.chip.VectorTable;
 
 const Core = enum {
@@ -1155,7 +1153,7 @@ pub const types = struct {
         /// System Timer (SysTick).
         pub const SysTick = extern struct {
             /// Control and Status Register.
-            CTRL: mmio.Mmio(packed struct(u32) {
+            CTRL: mmio.OldMmio(packed struct(u32) {
                 /// Enables the counter:
                 /// 0 = counter disabled.
                 /// 1 = counter enabled.
@@ -1176,20 +1174,20 @@ pub const types = struct {
                 reserved1: u15 = 0,
             }),
             /// Reload Value Register.
-            LOAD: mmio.Mmio(packed struct(u32) {
+            LOAD: mmio.OldMmio(packed struct(u32) {
                 /// Value to load into the VAL register when the counter is enabled and when it reaches 0.
                 RELOAD: u24,
                 reserved0: u8 = 0,
             }),
             /// Current Value Register.
-            VAL: mmio.Mmio(packed struct(u32) {
+            VAL: mmio.OldMmio(packed struct(u32) {
                 /// Reads return the current value of the SysTick counter.
                 /// A write of any value clears the field to 0, and also clears the CTRL.COUNTFLAG bit to 0.
                 CURRENT: u24,
                 reserved0: u8 = 0,
             }),
             /// Calibration Register.
-            CALIB: mmio.Mmio(packed struct(u32) {
+            CALIB: mmio.OldMmio(packed struct(u32) {
                 /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
                 /// reads as zero, the calibration value is not known.
                 TENMS: u24,

core/src/cpus/cortex_m/m0.zig

@@ -1,15 +1,13 @@
 const microzig = @import("microzig");
-const builtin = @import("builtin");
 const mmio = microzig.mmio;
-const shared = @import("shared_types.zig");
 
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -79,7 +77,7 @@ pub const SystemControlBlock = extern struct {
     }),
     reserved0: u32 = 0,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -101,7 +99,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct(u32) {
+    SCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
         /// 0 = do not sleep when returning to Thread mode.
@@ -130,7 +128,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u3 = 0,
         /// Always reads as one, indicates that all unaligned accesses generate a HardFault.
         UNALIGN_TRP: u1,

core/src/cpus/cortex_m/m0plus.zig

@@ -1,15 +1,13 @@
 const microzig = @import("microzig");
 const mmio = microzig.mmio;
 
-const shared = @import("shared_types.zig");
-
 pub const scb_base_offset = 0x0d00;
 
 pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         /// Contains the active exception number:
         /// 0 = Thread mode
         /// Nonzero = The exception number[a] of the currently active exception.
@@ -80,7 +78,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         /// Reserved for debug use. This bit reads as 0. When writing to the register you must
         /// write 0 to this bit, otherwise behavior is Unpredictable.
@@ -102,7 +100,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct(u32) {
+    SCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u1 = 0,
         /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
         /// 0 = do not sleep when returning to Thread mode.
@@ -131,7 +129,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         reserved0: u3 = 0,
         /// Always reads as one, indicates that all unaligned accesses generate a HardFault.
         UNALIGN_TRP: u1,
@@ -195,8 +193,8 @@ pub const NestedVectorInterruptController = extern struct {
 };
 
 pub const MemoryProtectionUnit = extern struct {
-    /// MPU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    /// MPU Type Register.
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -206,8 +204,8 @@ pub const MemoryProtectionUnit = extern struct {
         IREGION: u8,
         reserved1: u8 = 0,
     }),
-    /// MPU Control Register
-    CTRL: mmio.Mmio(packed struct(u32) {
+    /// MPU Control Register.
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -216,23 +214,23 @@ pub const MemoryProtectionUnit = extern struct {
         PRIVDEFENA: u1,
         reserved0: u29 = 0,
     }),
-    /// MPU Region Number Register
-    RNR: mmio.Mmio(packed struct(u32) {
+    /// MPU Region Number Register.
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
     }),
-    /// MPU Region Base Address Register
-    RBAR: mmio.Mmio(packed struct(u32) {
+    /// MPU Region Base Address Register.
+    RBAR: mmio.OldMmio(packed struct(u32) {
         /// MPU region field.
         REGION: u4,
         /// MPU region number valid bit.
         VALID: u1,
         /// Region base address field.
         ADDR: u27,
     }),
-    /// MPU Attribute and Size Register
-    RASR: mmio.Mmio(packed struct(u32) {
+    /// MPU Attribute and Size Register.
+    RASR: mmio.OldMmio(packed struct(u32) {
         /// Region enable bit.
         ENABLE: u1,
         /// Specifies the size of the MPU region. The minimum permitted value is 7 (b00111).

core/src/cpus/cortex_m/m3.zig

@@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
     /// CPUID Base Register.
     CPUID: u32,
     /// Interrupt Control and State Register.
-    ICSR: mmio.Mmio(packed struct(u32) {
+    ICSR: mmio.OldMmio(packed struct(u32) {
         VECTACTIVE: u9,
         reserved0: u2 = 0,
         RETTOBASE: u1,
@@ -28,7 +28,7 @@ pub const SystemControlBlock = extern struct {
     /// Vector Table Offset Register.
     VTOR: u32,
     /// Application Interrupt and Reset Control Register.
-    AIRCR: mmio.Mmio(packed struct {
+    AIRCR: mmio.OldMmio(packed struct {
         VECTRESET: u1,
         VECTCLRACTIVE: u1,
         SYSRESETREQ: u1,
@@ -39,7 +39,7 @@ pub const SystemControlBlock = extern struct {
         VECTKEY: u16,
     }),
     /// System Control Register.
-    SCR: mmio.Mmio(packed struct {
+    SCR: mmio.OldMmio(packed struct {
         reserved0: u1 = 0,
         SLEEPONEXIT: u1,
         SLEEPDEEP: u1,
@@ -48,7 +48,7 @@ pub const SystemControlBlock = extern struct {
         reserved2: u27 = 0,
     }),
     /// Configuration Control Register.
-    CCR: mmio.Mmio(packed struct(u32) {
+    CCR: mmio.OldMmio(packed struct(u32) {
         NONBASETHRDENA: u1,
         USERSETMPEND: u1,
         reserved0: u1 = 0,
@@ -62,9 +62,9 @@ pub const SystemControlBlock = extern struct {
     /// System Handlers Priority Registers.
     SHPR: [3]u32,
     /// System Handler Control and State Register.
-    SHCSR: mmio.Mmio(shared.scb.SHCSR),
+    SHCSR: mmio.OldMmio(shared.scb.SHCSR),
     /// Configurable Fault Status Register.
-    CFSR: mmio.Mmio(packed struct(u32) {
+    CFSR: mmio.OldMmio(packed struct(u32) {
         /// MemManage Fault Register.
         MMFSR: shared.scb.MMFSR,
         /// BusFault Status Register.
@@ -73,7 +73,7 @@ pub const SystemControlBlock = extern struct {
         UFSR: shared.scb.UFSR,
     }),
     /// HardFault Status Register.
-    HFSR: mmio.Mmio(shared.scb.HFSR),
+    HFSR: mmio.OldMmio(shared.scb.HFSR),
     reserved1: u32 = 0,
     /// MemManage Fault Address Register.
     MMFAR: u32,
@@ -108,7 +108,7 @@ pub const NestedVectorInterruptController = extern struct {
 
 pub const MemoryProtectionUnit = extern struct {
     /// MPU Type Register
-    TYPE: mmio.Mmio(packed struct(u32) {
+    TYPE: mmio.OldMmio(packed struct(u32) {
         /// Indicates support for unified or separate instructions and data address regions.
         SEPARATE: u1,
         reserved0: u7 = 0,
@@ -119,7 +119,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved1: u8 = 0,
     }),
     /// MPU Control Register
-    CTRL: mmio.Mmio(packed struct(u32) {
+    CTRL: mmio.OldMmio(packed struct(u32) {
         /// Enables the MPU
         ENABLE: u1,
         /// Enables of operation of MPU during HardFault and MNIHandlers.
@@ -129,7 +129,7 @@ pub const MemoryProtectionUnit = extern struct {
         reserved0: u29 = 0,
     }),
     /// MPU Region Number Register
-    RNR: mmio.Mmio(packed struct(u32) {
+    RNR: mmio.OldMmio(packed struct(u32) {
         /// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
         REGION: u8,
         reserved0: u24 = 0,
@@ -151,7 +151,7 @@ pub const MemoryProtectionUnit = extern struct {
     /// MPU Alias 3 Region Attribute and Size Register
     RASR_A3: RASR_Register,
 
-    pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
         /// MPU region field.
         REGION: u4,
         /// MPU region number valid bit.
@@ -160,7 +160,7 @@ pub const MemoryProtectionUnit = extern struct {
         ADDR: u27,
     });
 
-    pub const RASR_Register = mmio.Mmio(packed struct(u32) {
+    pub const RASR_Register = mmio.OldMmio(packed struct(u32) {
         /// Region enable bit.
         ENABLE: u1,
         /// Specifies the size of the MPU protection region.