Digital Verification Engineer by job, Open Source and AI Enthusiast by life.
- 🎓 2017-2021: 🇨🇳 B.Eng. EE (Fuxin 🚄 Harbin)
- 🎓 2021-2024: 🇩🇪 M.Sc. EE @ TUM (China
✈️ Munich) - 🧪 Internship: NeuSoft & Infineon
- 💼 2024-now: DV Engineer @ PlanV
中文创作者轮播图引擎。
把选题文案变成可渲染配置，并跑质量评分闭环。
DV playground for SV/UVM/Verilator/cocotb.
Practical examples for onboarding and quick experiments.
- 🚀 verilator: contribution-aligned work fork.
- 🧪 PlanV_Verilator_Feature_Tests: feature validation flow at work.
- 📘 MS_Thesis_cocotb-BSHL: thesis implementation repo.
- 📄 Advancing Open-Source Verification: Enabling Full Randomization in Verilator
DVcon Europe 2025 · Oct 15, 2025 - 📄 Enable Reuse of SystemVerilog Verification IPs in cocotb/pyuvm
DVcon Europe 2024 · Oct 16, 2024
- 📝 UVM in Verilator: Constraint random if/else
https://planv.tech/2024/08/02/enabling-uvm-support-in-verilator-series-part-1-constraint-random-ifelse-constraint-support/ - 📝 UVM in Verilator: CI system and test models
https://planv.tech/2024/10/08/enabling-uvm-support-in-verilator-series-our-ci-system-and-test-models/ - 📝 UVM in Verilator: Aggregate data type basic randomization
https://planv.tech/2024/11/07/enabling-uvm-support-in-verilator-series-basic-randomization-support-for-aggregate-data-types/ - 📝 UVM in Verilator: Array constrained randomization support
https://planv.tech/2025/02/07/enabling-uvm-support-in-verilator-series-constrained-randomization-support-for-all-types-of-arrays/ - 📝 UVM in Verilator: Struct constrained randomization support
https://planv.tech/2025/07/04/enabling-uvm-support-in-verilator-series-constrained-randomization-support-for-structs/ - 🤖 Verilator Gap Checker with AI
https://planv.tech/2026/02/24/verilator-gap-checker-automatically-detecting-feature-gaps-in-verilator-with-ai/
- 🧠
badai_cardsmith: 中文创作生产版（更多模板/系列）。 - 📚
ai-memoir: AI 回忆录系统（采访到交付）。 - 📝
story_engine: 中文故事引擎（主题到剧情）。 - 🎯
interview_helper: DV interview prep workflow.
- Email: wangyilou123@gmail.com