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Pull requests: Xilinx/mlir-aie
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[AIEPlacer] Read aie.buffer as tile-local memory capacity constraint
#3044
opened May 2, 2026 by
erwei-xilinx
Collaborator
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5 tasks done
[AIEPlacer] Read aie.cascade_flow as adjacency constraint
#3042
opened May 1, 2026 by
erwei-xilinx
Collaborator
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5 tasks done
[AIEPlacer] Read aie.flow / aie.packet_flow as channel-requirement and grouping sources
#3041
opened May 1, 2026 by
erwei-xilinx
Collaborator
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4 tasks done
[IRON] Add specialized FIFO subclasses (Cascade / Packet / Accum / Sparse / Memtile / VariableRate)
#3039
opened Apr 27, 2026 by
matteius
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3 of 5 tasks
Use tablegen Python bindings for trace events instead of separate generation
#3038
opened Apr 24, 2026 by
yenjames
Collaborator
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Fix overflow in number of bytes for long DMA BD lengths
#3034
opened Apr 17, 2026 by
andrej
Collaborator
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Expose set_aie_stream() on IRON ObjectFifo class
#2971
opened Mar 14, 2026 by
RobinMelhuish
Contributor
•
Draft
add aie-chess-simulation as examples for single core chess simulation in BFP16 and BF16
#2538
opened Aug 26, 2025 by
ChengyueWang
Contributor
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