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@parthash0804 parthash0804 commented Jan 21, 2026

Problem solved by the commit

  1. Support for multi hw context design on VE2 for AIE Trace and AIE Profile.
  2. VAIML design for VE2 now has IP_LAYOUT section in xclbin, XDP needs to differentiate that.

How problem was solved, alternative solutions (if any) and why they were rejected

  1. Column passed to XAIE Apis and FAL should be relative to the partition as aieDevice Instance already has shifted base address of the start column of that partition.
  2. For Telluride VAIML design assign device ID from 1 though xclbin type is AIE_PL because of IP_LAYOUT section in xclbin, as device ID 0 is fixed for PL or AIE_PL xclbin but VAIML design won't have PL section.

What has been tested and how, request additional testing if necessary

  1. AIE trace and profile for Multi hw_context design on Telluride
  2. AIE trace and profile for DSP design on Telluride
  3. AIE trace and profile on VCK190

…tion in xclbin

Signed-off-by: parthash0804 <ParthAshwin.Jain@amd.com>
…orrect aieDevice Instance.

Signed-off-by: parthash0804 <ParthAshwin.Jain@amd.com>
@parthash0804 parthash0804 changed the title Support for Multi hw_ctx on VE2 Support for Multi hw_ctx on VE2 for AIE Trace and AIE Profile Jan 21, 2026
@jvillarre jvillarre merged commit 2cd1e27 into Xilinx:master Jan 21, 2026
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2 participants