[RFC] target/riscv: iommu: Add GIPC Support #11
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Current implementation is wrong when iohgatp != bare. The RISC-V IOMMU specification has defined that the PDT is based on GPA, not SPA. So this patch fixes the problem, making PDT walk correctly when the G-stage table walk is enabled. Fixes: 0c54acb ("hw/riscv: add RISC-V IOMMU base emulation") Cc: Sebastien Boeuf <seb@rivosinc.com> Cc: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
GIPC: G-stage table In Process Context for IOMMU [1] (Not ratified). The motivation of GIPC is for virtualization of the Shared Work Queue or Atomic I/O Enqueue (AIOE) [2]. Here are the modifications summary: - Add GIPC feature bit in capability. - Add GIPC control bit in DC.tc. - Extend Process Context & PDT for GIPC. - Adjust Process Directory Table walk with SPA for GIPC. - Make PC.iohgatp & DC.iohgatp work together. [1] riscv-non-isa/riscv-iommu#413 [2] https://youtu.be/-fuqzYedOb0 Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
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GIPC: G-stage table In Process Context for IOMMU [1] (Not ratified).
The motivation of GIPC is for virtualization of the Shared Work Queue or Atomic I/O Enqueue (AIOE) [2].
Here are the modifications summary:
[1] riscv-non-isa/riscv-iommu#413
[2] https://youtu.be/-fuqzYedOb0
Second patch fixup PDT Nested Walk:
Current implementation is wrong when iohgatp != bare. The RISC-V IOMMU specification has defined that the PDT is based on GPA, not SPA. So this patch fixes the problem, making PDT walk correctly when the G-stage table walk is enabled.