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17e1038
Updating OpenROAD-flow-scripts Version
bgoldbug Dec 31, 2025
ee2a56f
Updated commit tag version for runorfs.sh
bgoldbug Dec 31, 2025
ee9e320
Updated git tag and tag abbreviation length for newer ORFS versions
bgoldbug Dec 31, 2025
9403267
Added github action to check necessary design files
bgoldbug Jan 5, 2026
5886110
Added file checks for git design check action
bgoldbug Jan 5, 2026
5d19e65
Separated bash list entries by white space
bgoldbug Jan 5, 2026
84ab51d
Adding updated asap7 config for NyuziProcessor design
bgoldbug Jan 7, 2026
9e1a8f7
Merge pull request #2 from bgoldbug/NyuziTest
bgoldbug Jan 7, 2026
5aaab10
Updating OpenROAD-flow-scripts Version
bgoldbug Dec 31, 2025
a144bf3
Updated commit tag version for runorfs.sh
bgoldbug Dec 31, 2025
7908ecd
Updated git tag and tag abbreviation length for newer ORFS versions
bgoldbug Dec 31, 2025
e2a2a5b
Added github action to check necessary design files
bgoldbug Jan 5, 2026
5ee12a6
Added file checks for git design check action
bgoldbug Jan 5, 2026
e703026
Separated bash list entries by white space
bgoldbug Jan 5, 2026
341ca33
Adding updated asap7 config for NyuziProcessor design
bgoldbug Jan 7, 2026
47c6edd
Adding changes to Nyuzi, added coralnpu, working on NVDLA
bgoldbug Feb 25, 2026
4350317
Adding coralnpu and NVDLA designs for asap7, update ORFS version
bgoldbug Mar 6, 2026
62f545e
Fixed merge conflicts
bgoldbug Mar 6, 2026
8f6775b
Update repo from upstream and change dev logic to update_rtl
bgoldbug Mar 11, 2026
8ee8c64
Added FakeRAM submodule
bgoldbug Mar 11, 2026
618db54
Update liteeth macros.v file and added Vortex design
bgoldbug Mar 12, 2026
6e3771b
Fixed Vortex slew violations
bgoldbug Mar 19, 2026
55ebc34
Tracked upstream repo changes (up-to-date)
bgoldbug Mar 19, 2026
3987644
Removed Nyuzi GPGPU (replaced with Vortex design)
bgoldbug Mar 19, 2026
3700228
Update update conditional inside verilog.mk (uses DO_UPDATE instead)
bgoldbug Mar 19, 2026
6228aee
Merge branch 'suite-update' into suite-update
bgoldbug Mar 19, 2026
d705135
Updated constraint.sdc and config.mk checking logic for GitHub actions
bgoldbug Mar 19, 2026
ed49ae5
Merge branch 'suite-update' of github.com:bgoldbug/UCSC_ML_suite-dev …
bgoldbug Mar 19, 2026
96caceb
GitHub actions adjustment for required file checks for designs
bgoldbug Mar 19, 2026
e05bc8e
Added required bp_processor LICENSE file
bgoldbug Mar 19, 2026
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164 changes: 164 additions & 0 deletions .github/workflows/require-design-files.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,164 @@
name: Validate PR designs

on:
pull_request:
types: [opened, synchronize, reopened, ready_for_review]
paths:
- "designs/**"

permissions:
contents: read

jobs:
validate:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
with:
fetch-depth: 0

- name: Validate required design files
shell: bash
run: |
set -euo pipefail

BASE_REF="origin/${{ github.base_ref }}"
HEAD_SHA="${{ github.sha }}"
git fetch origin "${{ github.base_ref }}" --no-tags --prune

techs=(sky130hd asap7 nangate45)

# Collect changed file paths for A/M (and treat R* as changed using new path field).
mapfile -t changed_paths < <(
git diff --name-status "${BASE_REF}...${HEAD_SHA}" \
| awk '
$1=="A" || $1=="M" {print $2}
$1 ~ /^R/ {print $3}
'
)

relevant_paths=()
for p in "${changed_paths[@]}"; do
if [[ "$p" =~ ^designs/src/[^/]+/ ]] || [[ "$p" =~ ^designs/[^/]+/[^/]+/ ]]; then
relevant_paths+=("$p")
fi
done

if (( ${#relevant_paths[@]} == 0 )); then
echo "No changes to designs/src/<design>/ or designs/<tech>/<design>/. Nothing to validate."
exit 0
fi

declare -A touched_src_design=() # key: <design>
declare -A touched_tech_design=() # key: <tech>/<design>

for p in "${changed_paths[@]}"; do
if [[ "$p" =~ ^designs/src/([^/]+)/ ]]; then
touched_src_design["${BASH_REMATCH[1]}"]=1
continue
fi

if [[ "$p" =~ ^designs/([^/]+)/([^/]+)/ ]]; then
t="${BASH_REMATCH[1]}"
d="${BASH_REMATCH[2]}"
for allowed in "${techs[@]}"; do
if [[ "$t" == "$allowed" ]]; then
touched_tech_design["$t/$d"]=1
break
fi
done
fi
done

echo "Design's with new or updated designs/src/ files:"
if (( ${#touched_src_design[@]} == 0 )); then
echo " - (none)"
else
for d in "${!touched_src_design[@]}"; do echo " - $d"; done
fi

echo "Design's with new/updated designs/<tech>/ files:"
if (( ${#touched_tech_design[@]} == 0 )); then
echo " - (none)"
else
for td in "${!touched_tech_design[@]}"; do echo " - $td"; done
fi

# REQUIRED files relative to designs/src/<design>/
required_src=(
"file:verilog.mk"
"file:LICENSE"
"dir:dev"
)

# REQUIRED files relative to designs/<tech>/<design>/
# Both config.mk and constraint.sdc are checked recursively (see below),
# so this list is intentionally empty but kept for future flat-check additions.
required_tech=()

missing=0

# Enforce src rules ONLY for src designs touched by PR
for d in "${!touched_src_design[@]}"; do
src_root="designs/src/$d"

# Require the directory itself
if [[ ! -d "$src_root" ]]; then
echo "::error file=designs/src::$src_root/ is required (touched by PR) but is missing."
missing=1
continue
fi

# Require files inside it
for req in "${required_src[@]}"; do
kind="${req%%:*}"
path="${req#*:}"

if [[ "$kind" == "file" ]]; then
if [[ ! -f "$src_root/$path" ]]; then
echo "::error file=$src_root/$path::Missing required file: $src_root/$path"
missing=1
fi
elif [[ "$kind" == "dir" ]]; then
if [[ ! -d "$src_root/$path" ]]; then
echo "::error file=$src_root/$path::Missing required directory: $src_root/$path/"
missing=1
fi
fi
done
done

# Enforce tech rules ONLY for tech/design trees touched by PR
for td in "${!touched_tech_design[@]}"; do
t="${td%%/*}"
d="${td#*/}"
tech_root="designs/$t/$d"

if [[ ! -d "$tech_root" ]]; then
echo "::error file=designs/$t::$tech_root/ is touched by PR but directory is missing."
missing=1
continue
fi

# Check required files recursively — each may live directly in <design>/ or in any subdir.
for req_file in config.mk constraint.sdc; do
if ! find "$tech_root" -name "$req_file" -type f -print -quit | grep -q .; then
echo "::error file=$tech_root::Missing required file: $req_file (expected anywhere under $tech_root/)"
missing=1
fi
done

for rel in "${required_tech[@]}"; do
if [[ ! -f "$tech_root/$rel" ]]; then
echo "::error file=$tech_root/$rel::Missing required file: $tech_root/$rel"
missing=1
fi
done
done

if (( missing )); then
echo "Validation failed."
exit 1
fi

echo "Validation passed."
15 changes: 14 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -8,4 +8,17 @@ objects
.dev*
.venv
sv2v
**/dev/liteeth_builds
**/dev/liteeth_builds
**/srecord/
**/bazel
**/sv2v*/
**/python-*/
**/systemc-*/
**/perl-*/
**/_build*/
**/openssl*/
**/_installed/
**/_tarballs/
**/*.log
**/packages/
**/generated/
16 changes: 13 additions & 3 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,19 @@
[submodule "designs/src/minimax/dev/repo"]
path = designs/src/minimax/dev/repo
url = https://github.com/gsmecher/minimax.git
[submodule "designs/src/NyuziProcessor/dev/repo"]
path = designs/src/NyuziProcessor/dev/repo
url = https://github.com/jbush001/NyuziProcessor.git
[submodule "designs/src/liteeth/dev/liteeth"]
path = designs/src/liteeth/dev/repo
url = https://github.com/enjoy-digital/liteeth.git
[submodule "designs/src/cnn/dev/repo"]
path = designs/src/cnn/dev/repo
url = https://github.com/NNgen/nngen
[submodule "designs/src/NVDLA/dev/repo"]
path = designs/src/NVDLA/dev/repo
url = https://github.com/nvdla/hw.git
branch = nv_small
[submodule "designs/src/coralnpu/dev/repo"]
path = designs/src/coralnpu/dev/repo
url = https://github.com/google-coral/coralnpu.git
[submodule "designs/src/gemmini/dev/repo"]
path = designs/src/gemmini/dev/repo
url = https://github.com/ucb-bar/gemmini.git
Expand All @@ -25,3 +29,9 @@
[submodule "designs/src/sha3/dev/repo"]
path = designs/src/sha3/dev/repo
url = https://github.com/ucb-bar/sha3
[submodule "FakeRAM"]
path = FakeRAM
url = https://github.com/VLSIDA/bsg_fakeram.git
[submodule "designs/src/vortex/dev/repo"]
path = designs/src/vortex/dev/repo
url = https://github.com/vortexgpgpu/vortex.git
1 change: 1 addition & 0 deletions FakeRAM
Submodule FakeRAM added at fae05c
69 changes: 17 additions & 52 deletions Makefile
Original file line number Diff line number Diff line change
@@ -1,70 +1,35 @@
### Comprehensive Design List (nangate45, sky130hd, asap7) ###
#
# DESIGN_CONFIG=./designs/nangate45/lfsr_prbs_gen/config.mk
#
# DESIGN_CONFIG=./designs/nangate45/minimax/config.mk
# DESIGN_CONFIG=./designs/nangate45/NyuziProcessor/config.mk
#
# DESIGN_CONFIG=./designs/sky130hd/lfsr_prbs_gen/config.mk
# DESIGN_CONFIG=./designs/sky130hd/minimax/config.mk
#
# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
# DESIGN_CONFIG=./designs/asap7/gemmini/config.mk
# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_a/config.mk
# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_c/config.mk
# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_m/config.mk
# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_o/config.mk
# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_p/config.mk
# DESIGN_CONFIG=./designs/asap7/coralnpu/config.mk
# DESIGN_CONFIG=./designs/asap7/minimax/config.mk
# DESIGN_CONFIG=./designs/asap7/lfsr_prbs_gen/config.mk
# DESIGN_CONFIG=./designs/asap7/NyuziProcessor/config.mk
# DESIGN_CONFIG=./designs/asap7/gemmini/config.mk
# DESIGN_CONFIG=./designs/asap7/bp_processor/bp_quad/config.mk

DESIGN_CONFIG ?= ./designs/nangate45/lfsr_prbs_gen/config.mk
DESIGN_CONFIG ?= ./designs/asap7/sha3/config.mk

-include OpenROAD-flow-scripts/flow/Makefile
# Designs with RAM macros use FakeRAM (LEF generated for pins, no internal logic)
# Check if calling "dev" with an ORFS command or by itself.
DEV_RUN_TAG?=x
.PHONY: dev
ifeq ($(firstword $(MAKECMDGOALS)),dev)
DEV_RUN_TAG:=$(shell date +%s%N)$(shell bash -c "echo $$RANDOM")
ifneq ($(lastword $(MAKECMDGOALS)),dev)
dev: ;@:
else
$(info Starting dev run)
dev: .dev-run-$(DESIGN_NAME)-$(DEV_RUN_TAG)
endif
endif
export DEV_RUN_TAG
.PHONY: update_rtl
update_rtl:
@$(MAKE) DO_UPDATE=1 do-update

.PHONY: do-dev-setup
do-dev-setup:
.PHONY: do-update
do-update:
git submodule init $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo
git submodule update $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo
# Check if a setup.sh script exists for the current design
@if [ -f "$(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh" ]; then \
bash $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh; \
fi

# .dev-suite-run flag is necessary because ORFS makefile unsets all vars for recursion
.DELETE_ON_ERROR:
.dev-run%:
# Change Design Nickname to avoid conflict between default and dev designs
: > $@
$(MAKE) do-dev-setup
@if [ ! -f "$(RESULTS_DIR)/1_synth.v" ]; then \
$(MAKE) finish; \
elif [ ! -f "$(RESULTS_DIR)/2_floorplan.odb" ]; then \
$(MAKE) do-floorplan do-place do-cts do-route do-finish; \
elif [ ! -f "$(RESULTS_DIR)/3_place.odb" ]; then \
$(MAKE) do-place do-cts do-route do-finish; \
elif [ ! -f "$(RESULTS_DIR)/4_cts.odb" ]; then \
$(MAKE) do-cts do-route do-finish; \
elif [ ! -f "$(RESULTS_DIR)/5_route.odb" ]; then \
$(MAKE) do-route do-finish; \
else \
$(MAKE) do-finish; \
fi
rm -f $@

.PHONY: clean_design

# DEV_SRC can be used to clean up any dev-dependent source files
clean_design:
rm -rf $(DEV_SRC)

clean_all: clean_design

@echo "Successfully updated Verilog RTL!"
2 changes: 1 addition & 1 deletion OpenROAD-flow-scripts
24 changes: 24 additions & 0 deletions designs/asap7/NVDLA/partition_a/config.mk
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
export DESIGN_NAME = NV_NVDLA_partition_a
export PLATFORM = asap7
export DESIGN_NICKNAME = NVDLA
export DESIGN_RESULTS_NAME = NVDLA_partition_a

-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk

export SYNTH_HIERARCHICAL = 1

export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_a/constraint.sdc

export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_256x16_1r1w.lef \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_272x16_1r1w.lef

export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_256x16_1r1w.lib \
$(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_272x16_1r1w.lib

export CORE_UTILIZATION = 55

export PLACE_DENSITY_LB_ADDON = 0.2

export MACRO_PLACE_HALO = 5 5

export TNS_END_PERCENT = 100
40 changes: 40 additions & 0 deletions designs/asap7/NVDLA/partition_a/constraint.sdc
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
# ===================================================================
# Using Contents of File: syn/cons/NV_NVDLA_partition_c.sdc
# NVDLA Open Source Project
#
# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the
# NVDLA Open Hardware License; see the "LICENSE.txt" file that came
# with this distribution for more information.
# ===================================================================
current_design NV_NVDLA_partition_a

set clk_name nvdla_core_clk
set clk_io_pct 0.2

set clk_port [get_ports $clk_name]

create_clock -name $clk_name -period 1500 -waveform {0 750} $clk_port
set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}]
set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}]
set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}]
set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}]



set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

set_input_delay [expr 1500 * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr 1500 * $clk_io_pct] -clock $clk_name [all_outputs]

set_ideal_network [get_ports direct_reset_]
set_ideal_network [get_ports dla_reset_rstn]
set_ideal_network -no_propagate [get_nets nvdla_core_rstn]
set_ideal_network [get_ports test_mode]

set_false_path -from [get_ports direct_reset_]
set_false_path -from [get_ports dla_reset_rstn]
set_false_path -from [get_ports test_mode]
set_false_path -from [get_ports pwrbus_ram_pd*]
set_false_path -from [get_ports tmc2slcg_disable_clock_gating]
set_false_path -from [get_ports global_clk_ovr_on]
set_false_path -from [get_ports nvdla_clk_ovr_on]
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