Feature/pcie#39
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@parhamsoltani you could also rebase your branch on top of Isn't PCIe interfacing defined by the PIPE interface (fabric side) and a group of LVDS' on the PCB side? Or is your proposal specific or independent of a vendor implementation. I though Xilinx offers a PIPE variant in their IP core. |
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The PCIe v4 VHDL implementation includes a common package defining link widths and Gen1–Gen4 speeds, TLP and DLLP types, flow control, LTSSM and power states, along with a core package providing transaction-layer interfaces and PHY lane definitions.
It aligns with AXI4/Avalon interface patterns, and resolves issue #33 as part of the High-Speed Serial Interfaces milestone.