Skip to content

Throw an exception if the user tries to render a trace without stepping the simulation #472

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
fdxmw merged 2 commits into from
May 26, 2026
+4 −7
Merged

Throw an exception if the user tries to render a trace without stepping the simulation #472

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
035854d
Throw an exception if the user tries to render a trace without steppi…
gaborszita Sep 7, 2025
ee9e9ff
Fix test error
gaborszita May 26, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions pyrtl/simulation.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1755,6 +1755,9 @@ def render_trace(
is not found in the map, the argument ``repr_func`` will be used instead.
:param segment_size: Traces are broken in the segments of this number of cycles.
"""
if len(self) == 0:
msg = "You need to step the simulation at least once to render a trace."
raise PyrtlError(msg)
if repr_per_name is None:
repr_per_name = {}
if _currently_in_jupyter_notebook():
Expand Down
8 changes: 1 addition & 7 deletions tests/test_compilesim.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1206,14 +1206,8 @@ def test_empty_trace_after_untraceable_removed(self):
r.next <<= r + 1
sim = self.sim()
sim.step_multiple(provided_inputs={}, nsteps=10)
with self.assertRaises(pyrtl.PyrtlError) as ex:
with self.assertRaises(pyrtl.PyrtlError):
sim.tracer.render_trace()
self.assertEqual(
str(ex.exception),
"Empty trace list. This may have occurred because "
"untraceable wires were removed prior to simulation, "
"if a CompiledSimulation was used.",
)

def test_invalid_base(self):
self.in1 = pyrtl.Input(8, "in1")
Expand Down
Loading