Add ihp-sg13cmos5l

.gitignore

@@ -57,6 +57,7 @@ flow/*.opennet
 flow/platforms/*
 !flow/platforms/asap7
 !flow/platforms/ihp-sg13g2
+!flow/platforms/ihp-sg13cmos5l
 !flow/platforms/nangate45
 !flow/platforms/sky130hd
 !flow/platforms/sky130hs

flow/designs/ihp-sg13cmos5l/aes/autotuner.json

@@ -0,0 +1,84 @@
+{
+    "_SDC_FILE_PATH": "constraint.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            4.0,
+            6.0
+        ],
+        "step": 0
+    },
+    "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            20,
+            50
+        ],
+        "step": 1
+    },
+    "CORE_ASPECT_RATIO": {
+        "type": "float",
+        "minmax": [
+            0.5,
+            2.0
+        ],
+        "step": 0
+    },
+    "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "_FR_LAYER_ADJUST": {
+        "type": "float",
+        "minmax": [
+            0.1,
+            0.3
+        ],
+        "step": 0
+    },
+    "PLACE_DENSITY_LB_ADDON": {
+        "type": "float",
+        "minmax": [
+            0.0,
+            0.2
+        ],
+        "step": 0
+    },
+    "_PINS_DISTANCE": {
+        "type": "int",
+        "minmax": [
+            1,
+            4
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_SIZE": {
+        "type": "int",
+        "minmax": [
+            10,
+            200
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_DIAMETER": {
+        "type": "int",
+        "minmax": [
+            20,
+            400
+        ],
+        "step": 1
+    },
+    "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl"
+}

flow/designs/ihp-sg13cmos5l/aes/config.mk

@@ -0,0 +1,16 @@
+export DESIGN_NICKNAME = aes
+export DESIGN_NAME = aes_cipher_top
+export PLATFORM    = ihp-sg13cmos5l
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export CORE_UTILIZATION = 20 
+export CORE_ASPECT_RATIO = 1
+
+export PLACE_DENSITY = 0.65
+export TNS_END_PERCENT = 100
+
+export USE_FILL = 1
+
+export REMOVE_ABC_BUFFERS = 1

flow/designs/ihp-sg13cmos5l/aes/constraint.sdc

@@ -0,0 +1,15 @@
+current_design aes_cipher_top
+
+set clk_name clk
+set clk_port_name clk
+set clk_period 4.5
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/ihp-sg13cmos5l/aes/rules-base.json

@@ -0,0 +1,102 @@
+{
+    "synth__design__instance__area__stdcell": {
+        "value": 214000.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 1,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 200905,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 18614,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 1128,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 1128,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 782983,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 1,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -0.225,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -0.9,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 204761,
+        "compare": "<="
+    }
+}

flow/designs/ihp-sg13cmos5l/gcd/autotuner.json

@@ -0,0 +1,84 @@
+{
+    "_SDC_FILE_PATH": "constraint.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            2.0,
+            12.0
+        ],
+        "step": 0
+    },
+    "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            15,
+            50
+        ],
+        "step": 1
+    },
+    "CORE_ASPECT_RATIO": {
+        "type": "float",
+        "minmax": [
+            0.5,
+            2.0
+        ],
+        "step": 0
+    },
+    "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "_FR_LAYER_ADJUST": {
+        "type": "float",
+        "minmax": [
+            0.1,
+            0.3
+        ],
+        "step": 0
+    },
+    "PLACE_DENSITY_LB_ADDON": {
+        "type": "float",
+        "minmax": [
+            0.0,
+            0.2
+        ],
+        "step": 0
+    },
+    "_PINS_DISTANCE": {
+        "type": "int",
+        "minmax": [
+            1,
+            3
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_SIZE": {
+        "type": "int",
+        "minmax": [
+            10,
+            200
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_DIAMETER": {
+        "type": "int",
+        "minmax": [
+            20,
+            400
+        ],
+        "step": 1
+    },
+    "_FR_FILE_PATH": "../../../platforms/ihp-sg13g2/fastroute.tcl"
+}

flow/designs/ihp-sg13cmos5l/gcd/config.mk

@@ -0,0 +1,14 @@
+export DESIGN_NAME = gcd
+export PLATFORM    = ihp-sg13cmos5l
+
+export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v
+export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export USE_FILL = 1
+
+export PLACE_DENSITY ?= 0.88
+export CORE_UTILIZATION = 20
+export TNS_END_PERCENT = 100
+
+export SWAP_ARITH_OPERATORS = 1
+export OPENROAD_HIERARCHICAL = 1

flow/designs/ihp-sg13cmos5l/gcd/constraint.sdc

@@ -0,0 +1,15 @@
+current_design gcd
+
+set clk_name core_clock
+set clk_port_name clk
+set clk_period 2.8
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]