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Fixed test RE's #15

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Merged
maliberty merged 1 commit into from
Jan 15, 2026
Merged

Fixed test RE's #15

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2 changes: 1 addition & 1 deletion test/basic_port_creator_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ def setUp(self):

self._process = Process(TestUtils.get_base_process_data())
self._timing_data = TimingData()
self._rect_re = re.compile("^\s*RECT\s+(\S+)\s+(\S+)\s+(\S+)\s+(\S+)\s+\;")
self._rect_re = re.compile(r"^\s*RECT\s+(\S+)\s+(\S+)\s+(\S+)\s+(\S+)\s+\;")
self._start_y = 0.48
self._start_pitch = 0.0
self._threshold = 0.001
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10 changes: 5 additions & 5 deletions test/flow_test.py
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Expand Up @@ -22,11 +22,11 @@ def setUp(self):
self._results_dir = os.path.join(self._test_dir, "results")
if os.path.isdir(self._results_dir):
shutil.rmtree(self._results_dir)
self._macro_re = re.compile("^MACRO\s+(\S+)")
self._size_re = re.compile("^\s+SIZE\s+(\S+)\s+BY\s+(\S+)")
self._start_pin_re = re.compile("^\s+PIN\s+(\S+)")
self._macro_name_re = re.compile("\S+_(\d+)x(\d+)")
self._pin_dir_re = re.compile("^\s*DIRECTION\s+(\S+)")
self._macro_re = re.compile(r"^MACRO\s+(\S+)")
self._size_re = re.compile(r"^\s+SIZE\s+(\S+)\s+BY\s+(\S+)")
self._start_pin_re = re.compile(r"^\s+PIN\s+(\S+)")
self._macro_name_re = re.compile(r"\S+_(\d+)x(\d+)")
self._pin_dir_re = re.compile(r"^\s*DIRECTION\s+(\S+)")

def _getLefPin(self, fh, pin_name):
"""Extracts data for given LEF pin and returns it in a dict"""
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2 changes: 1 addition & 1 deletion test/sv_bbox_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ def setUp(self):
self._process = Process(TestUtils.get_base_process_data())
self._timing_data = TimingData()
self._bus_re = re.compile(
"^\s*\S+\s+(?:reg)?\s*\[\s*(\d+)\:(\d+)\\s*]\s*(\S+)\s*\,"
r"^\s*\S+\s+(?:reg)?\s*\[\s*(\d+)\:(\d+)\s*]\s*(\S+)\s*\,"
)

def _extract_bus_msb(self, content):
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2 changes: 1 addition & 1 deletion utils/ss_port_organizer.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ def __init__(self, pin_type_map):
self._misc_busses = []
self._misc_ports = []
self._port_dict = {}
self._bus_name_re = re.compile("^(\S+)\[(\d+)\]")
self._bus_name_re = re.compile(r"^(\S+)\[(\d+)\]")
self._pin_type_map = pin_type_map

def get_rw_groups(self):
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