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Fix write logic in SP model #14

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Merged
maliberty merged 1 commit into from
Jan 15, 2026
Merged

Fix write logic in SP model #14

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2 changes: 1 addition & 1 deletion test/au/spsram_256x256.au
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Original file line number Diff line number Diff line change
Expand Up @@ -5008,7 +5008,7 @@ module spsram_256x256
end
else if (we_in)
begin
mem[addr_in] <= (wd_in) | (mem[addr_in]);
mem[addr_in] <= wd_in;
end
// read
rd_out <= mem[addr_in];
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2 changes: 1 addition & 1 deletion test/au/spsram_256x32.au
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Original file line number Diff line number Diff line change
Expand Up @@ -867,7 +867,7 @@ module spsram_256x32
end
else if (we_in)
begin
mem[addr_in] <= (wd_in) | (mem[addr_in]);
mem[addr_in] <= wd_in;
end
// read
rd_out <= mem[addr_in];
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2 changes: 1 addition & 1 deletion test/au/spsram_256x32_h.au
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Original file line number Diff line number Diff line change
Expand Up @@ -874,7 +874,7 @@ module spsram_256x32_h
end
else if (we_in)
begin
mem[addr_in] <= (wd_in) | (mem[addr_in]);
mem[addr_in] <= wd_in;
end
// read
rd_out <= mem[addr_in];
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2 changes: 1 addition & 1 deletion utils/single_port_ram_verilog_exporter.py
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Expand Up @@ -60,7 +60,7 @@ def export_module(self, out_fh):
out_fh.write(f" else if ({we_pin})\n")
out_fh.write(" begin\n")
out_fh.write(
f" mem[{addr_bus}] <= ({din_bus}) | (mem[{addr_bus}]);\n"
f" mem[{addr_bus}] <= {din_bus};\n"
)
out_fh.write(" end\n")
out_fh.write(" // read\n")
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