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2,919 changes: 1,474 additions & 1,445 deletions test/au/dprf_256x256.au

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569 changes: 299 additions & 270 deletions test/au/dprf_256x32.au

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583 changes: 306 additions & 277 deletions test/au/dprf_256x32_h.au

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2,921 changes: 1,475 additions & 1,446 deletions test/au/dpsram_256x256.au

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571 changes: 300 additions & 271 deletions test/au/dpsram_256x32.au

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589 changes: 309 additions & 280 deletions test/au/dpsram_256x32_h.au

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780 changes: 390 additions & 390 deletions test/au/sprf_256x256.au

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224 changes: 112 additions & 112 deletions test/au/sprf_256x32.au

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274 changes: 137 additions & 137 deletions test/au/sprf_256x32_h.au

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240 changes: 120 additions & 120 deletions test/au/spsram_256x256.au
Original file line number Diff line number Diff line change
Expand Up @@ -4703,24 +4703,140 @@ MACRO spsram_256x256
RECT 0.000 83.424 0.024 83.448 ;
END
END we_in
PIN ce_in
PIN clk
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 83.568 0.024 83.592 ;
END
END ce_in
PIN clk
END clk
PIN ce_in
DIRECTION INPUT ;
USE SIGNAL ;
SHAPE ABUTMENT ;
PORT
LAYER M4 ;
RECT 0.000 83.712 0.024 83.736 ;
END
END clk
END ce_in
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M4 ;
RECT 0.048 0.384 33.202 0.480 ;
RECT 0.048 1.152 33.202 1.248 ;
RECT 0.048 1.920 33.202 2.016 ;
RECT 0.048 2.688 33.202 2.784 ;
RECT 0.048 3.456 33.202 3.552 ;
RECT 0.048 4.224 33.202 4.320 ;
RECT 0.048 4.992 33.202 5.088 ;
RECT 0.048 5.760 33.202 5.856 ;
RECT 0.048 6.528 33.202 6.624 ;
RECT 0.048 7.296 33.202 7.392 ;
RECT 0.048 8.064 33.202 8.160 ;
RECT 0.048 8.832 33.202 8.928 ;
RECT 0.048 9.600 33.202 9.696 ;
RECT 0.048 10.368 33.202 10.464 ;
RECT 0.048 11.136 33.202 11.232 ;
RECT 0.048 11.904 33.202 12.000 ;
RECT 0.048 12.672 33.202 12.768 ;
RECT 0.048 13.440 33.202 13.536 ;
RECT 0.048 14.208 33.202 14.304 ;
RECT 0.048 14.976 33.202 15.072 ;
RECT 0.048 15.744 33.202 15.840 ;
RECT 0.048 16.512 33.202 16.608 ;
RECT 0.048 17.280 33.202 17.376 ;
RECT 0.048 18.048 33.202 18.144 ;
RECT 0.048 18.816 33.202 18.912 ;
RECT 0.048 19.584 33.202 19.680 ;
RECT 0.048 20.352 33.202 20.448 ;
RECT 0.048 21.120 33.202 21.216 ;
RECT 0.048 21.888 33.202 21.984 ;
RECT 0.048 22.656 33.202 22.752 ;
RECT 0.048 23.424 33.202 23.520 ;
RECT 0.048 24.192 33.202 24.288 ;
RECT 0.048 24.960 33.202 25.056 ;
RECT 0.048 25.728 33.202 25.824 ;
RECT 0.048 26.496 33.202 26.592 ;
RECT 0.048 27.264 33.202 27.360 ;
RECT 0.048 28.032 33.202 28.128 ;
RECT 0.048 28.800 33.202 28.896 ;
RECT 0.048 29.568 33.202 29.664 ;
RECT 0.048 30.336 33.202 30.432 ;
RECT 0.048 31.104 33.202 31.200 ;
RECT 0.048 31.872 33.202 31.968 ;
RECT 0.048 32.640 33.202 32.736 ;
RECT 0.048 33.408 33.202 33.504 ;
RECT 0.048 34.176 33.202 34.272 ;
RECT 0.048 34.944 33.202 35.040 ;
RECT 0.048 35.712 33.202 35.808 ;
RECT 0.048 36.480 33.202 36.576 ;
RECT 0.048 37.248 33.202 37.344 ;
RECT 0.048 38.016 33.202 38.112 ;
RECT 0.048 38.784 33.202 38.880 ;
RECT 0.048 39.552 33.202 39.648 ;
RECT 0.048 40.320 33.202 40.416 ;
RECT 0.048 41.088 33.202 41.184 ;
RECT 0.048 41.856 33.202 41.952 ;
RECT 0.048 42.624 33.202 42.720 ;
RECT 0.048 43.392 33.202 43.488 ;
RECT 0.048 44.160 33.202 44.256 ;
RECT 0.048 44.928 33.202 45.024 ;
RECT 0.048 45.696 33.202 45.792 ;
RECT 0.048 46.464 33.202 46.560 ;
RECT 0.048 47.232 33.202 47.328 ;
RECT 0.048 48.000 33.202 48.096 ;
RECT 0.048 48.768 33.202 48.864 ;
RECT 0.048 49.536 33.202 49.632 ;
RECT 0.048 50.304 33.202 50.400 ;
RECT 0.048 51.072 33.202 51.168 ;
RECT 0.048 51.840 33.202 51.936 ;
RECT 0.048 52.608 33.202 52.704 ;
RECT 0.048 53.376 33.202 53.472 ;
RECT 0.048 54.144 33.202 54.240 ;
RECT 0.048 54.912 33.202 55.008 ;
RECT 0.048 55.680 33.202 55.776 ;
RECT 0.048 56.448 33.202 56.544 ;
RECT 0.048 57.216 33.202 57.312 ;
RECT 0.048 57.984 33.202 58.080 ;
RECT 0.048 58.752 33.202 58.848 ;
RECT 0.048 59.520 33.202 59.616 ;
RECT 0.048 60.288 33.202 60.384 ;
RECT 0.048 61.056 33.202 61.152 ;
RECT 0.048 61.824 33.202 61.920 ;
RECT 0.048 62.592 33.202 62.688 ;
RECT 0.048 63.360 33.202 63.456 ;
RECT 0.048 64.128 33.202 64.224 ;
RECT 0.048 64.896 33.202 64.992 ;
RECT 0.048 65.664 33.202 65.760 ;
RECT 0.048 66.432 33.202 66.528 ;
RECT 0.048 67.200 33.202 67.296 ;
RECT 0.048 67.968 33.202 68.064 ;
RECT 0.048 68.736 33.202 68.832 ;
RECT 0.048 69.504 33.202 69.600 ;
RECT 0.048 70.272 33.202 70.368 ;
RECT 0.048 71.040 33.202 71.136 ;
RECT 0.048 71.808 33.202 71.904 ;
RECT 0.048 72.576 33.202 72.672 ;
RECT 0.048 73.344 33.202 73.440 ;
RECT 0.048 74.112 33.202 74.208 ;
RECT 0.048 74.880 33.202 74.976 ;
RECT 0.048 75.648 33.202 75.744 ;
RECT 0.048 76.416 33.202 76.512 ;
RECT 0.048 77.184 33.202 77.280 ;
RECT 0.048 77.952 33.202 78.048 ;
RECT 0.048 78.720 33.202 78.816 ;
RECT 0.048 79.488 33.202 79.584 ;
RECT 0.048 80.256 33.202 80.352 ;
RECT 0.048 81.024 33.202 81.120 ;
RECT 0.048 81.792 33.202 81.888 ;
RECT 0.048 82.560 33.202 82.656 ;
RECT 0.048 83.328 33.202 83.424 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
Expand Down Expand Up @@ -4838,122 +4954,6 @@ MACRO spsram_256x256
RECT 0.048 83.712 33.202 83.808 ;
END
END VSS
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M4 ;
RECT 0.048 0.384 33.202 0.480 ;
RECT 0.048 1.152 33.202 1.248 ;
RECT 0.048 1.920 33.202 2.016 ;
RECT 0.048 2.688 33.202 2.784 ;
RECT 0.048 3.456 33.202 3.552 ;
RECT 0.048 4.224 33.202 4.320 ;
RECT 0.048 4.992 33.202 5.088 ;
RECT 0.048 5.760 33.202 5.856 ;
RECT 0.048 6.528 33.202 6.624 ;
RECT 0.048 7.296 33.202 7.392 ;
RECT 0.048 8.064 33.202 8.160 ;
RECT 0.048 8.832 33.202 8.928 ;
RECT 0.048 9.600 33.202 9.696 ;
RECT 0.048 10.368 33.202 10.464 ;
RECT 0.048 11.136 33.202 11.232 ;
RECT 0.048 11.904 33.202 12.000 ;
RECT 0.048 12.672 33.202 12.768 ;
RECT 0.048 13.440 33.202 13.536 ;
RECT 0.048 14.208 33.202 14.304 ;
RECT 0.048 14.976 33.202 15.072 ;
RECT 0.048 15.744 33.202 15.840 ;
RECT 0.048 16.512 33.202 16.608 ;
RECT 0.048 17.280 33.202 17.376 ;
RECT 0.048 18.048 33.202 18.144 ;
RECT 0.048 18.816 33.202 18.912 ;
RECT 0.048 19.584 33.202 19.680 ;
RECT 0.048 20.352 33.202 20.448 ;
RECT 0.048 21.120 33.202 21.216 ;
RECT 0.048 21.888 33.202 21.984 ;
RECT 0.048 22.656 33.202 22.752 ;
RECT 0.048 23.424 33.202 23.520 ;
RECT 0.048 24.192 33.202 24.288 ;
RECT 0.048 24.960 33.202 25.056 ;
RECT 0.048 25.728 33.202 25.824 ;
RECT 0.048 26.496 33.202 26.592 ;
RECT 0.048 27.264 33.202 27.360 ;
RECT 0.048 28.032 33.202 28.128 ;
RECT 0.048 28.800 33.202 28.896 ;
RECT 0.048 29.568 33.202 29.664 ;
RECT 0.048 30.336 33.202 30.432 ;
RECT 0.048 31.104 33.202 31.200 ;
RECT 0.048 31.872 33.202 31.968 ;
RECT 0.048 32.640 33.202 32.736 ;
RECT 0.048 33.408 33.202 33.504 ;
RECT 0.048 34.176 33.202 34.272 ;
RECT 0.048 34.944 33.202 35.040 ;
RECT 0.048 35.712 33.202 35.808 ;
RECT 0.048 36.480 33.202 36.576 ;
RECT 0.048 37.248 33.202 37.344 ;
RECT 0.048 38.016 33.202 38.112 ;
RECT 0.048 38.784 33.202 38.880 ;
RECT 0.048 39.552 33.202 39.648 ;
RECT 0.048 40.320 33.202 40.416 ;
RECT 0.048 41.088 33.202 41.184 ;
RECT 0.048 41.856 33.202 41.952 ;
RECT 0.048 42.624 33.202 42.720 ;
RECT 0.048 43.392 33.202 43.488 ;
RECT 0.048 44.160 33.202 44.256 ;
RECT 0.048 44.928 33.202 45.024 ;
RECT 0.048 45.696 33.202 45.792 ;
RECT 0.048 46.464 33.202 46.560 ;
RECT 0.048 47.232 33.202 47.328 ;
RECT 0.048 48.000 33.202 48.096 ;
RECT 0.048 48.768 33.202 48.864 ;
RECT 0.048 49.536 33.202 49.632 ;
RECT 0.048 50.304 33.202 50.400 ;
RECT 0.048 51.072 33.202 51.168 ;
RECT 0.048 51.840 33.202 51.936 ;
RECT 0.048 52.608 33.202 52.704 ;
RECT 0.048 53.376 33.202 53.472 ;
RECT 0.048 54.144 33.202 54.240 ;
RECT 0.048 54.912 33.202 55.008 ;
RECT 0.048 55.680 33.202 55.776 ;
RECT 0.048 56.448 33.202 56.544 ;
RECT 0.048 57.216 33.202 57.312 ;
RECT 0.048 57.984 33.202 58.080 ;
RECT 0.048 58.752 33.202 58.848 ;
RECT 0.048 59.520 33.202 59.616 ;
RECT 0.048 60.288 33.202 60.384 ;
RECT 0.048 61.056 33.202 61.152 ;
RECT 0.048 61.824 33.202 61.920 ;
RECT 0.048 62.592 33.202 62.688 ;
RECT 0.048 63.360 33.202 63.456 ;
RECT 0.048 64.128 33.202 64.224 ;
RECT 0.048 64.896 33.202 64.992 ;
RECT 0.048 65.664 33.202 65.760 ;
RECT 0.048 66.432 33.202 66.528 ;
RECT 0.048 67.200 33.202 67.296 ;
RECT 0.048 67.968 33.202 68.064 ;
RECT 0.048 68.736 33.202 68.832 ;
RECT 0.048 69.504 33.202 69.600 ;
RECT 0.048 70.272 33.202 70.368 ;
RECT 0.048 71.040 33.202 71.136 ;
RECT 0.048 71.808 33.202 71.904 ;
RECT 0.048 72.576 33.202 72.672 ;
RECT 0.048 73.344 33.202 73.440 ;
RECT 0.048 74.112 33.202 74.208 ;
RECT 0.048 74.880 33.202 74.976 ;
RECT 0.048 75.648 33.202 75.744 ;
RECT 0.048 76.416 33.202 76.512 ;
RECT 0.048 77.184 33.202 77.280 ;
RECT 0.048 77.952 33.202 78.048 ;
RECT 0.048 78.720 33.202 78.816 ;
RECT 0.048 79.488 33.202 79.584 ;
RECT 0.048 80.256 33.202 80.352 ;
RECT 0.048 81.024 33.202 81.120 ;
RECT 0.048 81.792 33.202 81.888 ;
RECT 0.048 82.560 33.202 82.656 ;
RECT 0.048 83.328 33.202 83.424 ;
END
END VDD
OBS
LAYER M1 ;
RECT 0 0 33.250 84.000 ;
Expand Down
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