Building a RISC-V CPU Core

Build a RISC-V CPU core with TL-Verilog

How to start

Install makerchip IDE

pip3 install makerchip-app

Run makerchip IDE

makerchip riscv.tlv

Implementation plan

Chapter 4. RISC-V-Subset CPU

1. PC logic

2. Fetch

3. Decode logic

4. Register file read

5. ALU
6. Register file write

7. Branch logic

Instruction	Meaning	Condition Expression
BEQ	Branch if equal	x1 == x2
BNE	Branch if not equal	x1 != x2
BLT	Branch if less than	(x1 < x2) ^ (x1[31] != x2[31])
BGE	Branch if greater than or equal	(x1 >= x2) ^ (x1[31] != x2[31])
BLTU	Branch if less than, unsigned	x1 < x2
BGEU	Branch if greater than or equal, unsigned	x1 >= x2

Chapter 5. Completing Your RISC-V CPU

8. Decode logic

9. ALU

RISC-V green card

10. Jump logic
11. DMem