capri1_mx_faultanalysis

A fault-injection harness for five 8-bit microscaling (MX) numeric encodings on the CAPRI1 RISC-V SoC, written for the GLSVLSI 2026 publication by Shanmugam & Schaumont (WPI).

This repository contains the technology-independent portion of the work: training, quantization, firmware sources, the host fault sweep, the simulation harness, and the table/figure generators.

Sister silicon repository: https://github.com/Secure-Embedded-Systems/capri1_ets

Repository layout

• 1_train/ — PyTorch training and ONNX export for the four workloads (E1 self-attention, E2 mixture-of-experts attention, E3 MLP, E4 keyword-spotting attention).
• 2_quantize/ — MX block quantization (k = 4) producing C headers consumed by the firmware.
• 3_firmware/ — Five MX-format C kernels × four workloads = 20 RV32IC firmware variants. Each binary fits the 1 KB SRAM budget.
  • common/mx_formats.h — MXINT8, MXFP8-E4M3, MXFP8-E5M2, LOG8-SUM, LOG8-MAX decoders and per-format MAC kernels.
• 4_sim/ — Testbench, scan-chain definition, fault-injection scripts, and a Verilator lint path for the RTL.
• 5_fault/ — Python fault-injection harness, host-compiled C bridge (c_runner/runner.c + librunner.so), Python-vs-C bit-equality regression, scan-frame Hamming-distance parser.
• 6_results/ — Per-fault CSV outputs (campaign_sim_e1.csv, campaign_behavioral_*.csv, etc.).
• 7_aggregate/ — Table and figure generators driven by the CSVs.
• verified/ — Self-contained subtree that re-runs the LOG8-MAX sweep end-to-end with only gcc and python3.
• tables/, figures/ — Generated TeX tables and figures.
• Makefile — Top-level driver.

How to run

Quick path (≈ 60 seconds, no toolchain)

# 1. Render tables and figures from the CSVs that ship in the repo.
make mx figures
ls tables/ figures/

# 2. Re-run the end-to-end LOG8-MAX sweep.
cd verified
gcc -O2 -fPIC -shared -o backend_host/librunner.so backend_host/runner.c
python3 sweep/host_fault_sweep_all_formats.py

Full pipeline (toolchain required)

make firmware   # build 20 RV32IC binaries (≤ 1 KB SRAM each)
make fault      # Python + host-C fault sweeps over every weight bit
make aggregate  # regenerate tables and figures

Prerequisites

Component	Minimum	Used in
Python	3.8	5_fault/, 7_aggregate/, 1_train/, 2_quantize/
numpy	any	quantization, aggregation
pytorch	1.10 (optional)	training (.pt files are pre-staged)
onnx, onnxruntime	1.10 (optional)	export only
matplotlib	any (optional)	figures (TeX fallback if absent)
riscv64-unknown-elf-gcc	12+	RV32IC firmware build
verilator	recent	RTL lint at 4_sim/scripts/verilator_lint.sh

If a toolchain is absent the corresponding phase prints MISSING_TOOLCHAIN: ... and continues.

Workloads

Tag	Workload	Weights	Fault sites / format
E1	Self-Attention (Tiny Attention)	28	280 (7 SE × 8 + 28 elem × 8)
E2	MoE Attention (max-gate)	28	280
E3	MLP anomaly detector	114	912
E4	KWS Attention (4 tokens)	106	848

The CAPRI1 physical chip and its synthesised netlist are not part of this repository.

Citation

Shanmugam, D. and Schaumont, P. (2026). Fault Analysis of Microscaling Formats on a RISC-V SoC. Proceedings of the Great Lakes Symposium on VLSI 2026 (GLSVLSI '26). ACM. https://doi.org/10.1145/3787109.3815291.

@inproceedings{Shanmugam2026MXFault,
  author    = {Dillibabu Shanmugam and Patrick Schaumont},
  title     = {Fault Analysis of Microscaling Formats on a {RISC-V} {SoC}},
  booktitle = {Proceedings of the Great Lakes Symposium on VLSI 2026 (GLSVLSI)},
  year      = {2026},
  doi       = {10.1145/3787109.3815291}
}

License

Apache-2.0 (see LICENSE). The CROC linker (3_firmware/soc/link.ld) and crt0 (3_firmware/soc/crt0.S) are derivative works of the CROC platform from ETH Zurich and University of Bologna under the same license.

Acknowledgements

This research was supported in part by the National Science Foundation under Grant No. 2219810.