Merge to tag jdk-27+21

make/autoconf/jdk-options.m4

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2025, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2026, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -323,6 +323,14 @@ AC_DEFUN_ONCE([JDKOPT_SETUP_DEBUG_SYMBOLS],
   AC_SUBST(COPY_DEBUG_SYMBOLS)
   AC_SUBST(ZIP_EXTERNAL_DEBUG_SYMBOLS)
 
+  # Should we enable objcopy debuginfo compression ?
+  UTIL_ARG_ENABLE(NAME: objcopy-debuginfo-compression, DEFAULT: false,
+      RESULT: ENABLE_OBJCOPY_DEBUGINFO_COMPRESSION,
+      DESC: [Set to enable compression in the debuginfo files (Linux only)],
+      CHECKING_MSG: [if debuginfo compression with objcopy is done],
+      IF_ENABLED: [ OBJCOPY_COMPRESS_FLAGS="--compress-debug-sections=zlib-gnu" ])
+  AC_SUBST(OBJCOPY_COMPRESS_FLAGS)
+
   # Should we add external native debug symbols to the shipped bundles?
   AC_MSG_CHECKING([if we should add external native debug symbols to the shipped bundles])
   AC_ARG_WITH([external-symbols-in-bundles],

make/autoconf/spec.gmk.template

@@ -635,6 +635,7 @@ METALLIB := @METALLIB@
 COMPILE_WITH_DEBUG_SYMBOLS := @COMPILE_WITH_DEBUG_SYMBOLS@
 COPY_DEBUG_SYMBOLS := @COPY_DEBUG_SYMBOLS@
 ZIP_EXTERNAL_DEBUG_SYMBOLS := @ZIP_EXTERNAL_DEBUG_SYMBOLS@
+OBJCOPY_COMPRESS_FLAGS := @OBJCOPY_COMPRESS_FLAGS@
 
 CFLAGS_DEBUG_SYMBOLS := @CFLAGS_DEBUG_SYMBOLS@
 ASFLAGS_DEBUG_SYMBOLS := @ASFLAGS_DEBUG_SYMBOLS@

make/common/native/Link.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2025, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2026, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -189,7 +189,7 @@ define CreateDynamicLibraryOrExecutable
             # This cannot be run separately since it updates the original target
             # file.
 	    $$(call ExecuteWithLog, $$($1_OBJECT_DIR)/$$($1_SAFE_NAME)_create_debuginfo, \
-	        $$($1_OBJCOPY) --only-keep-debug $$($1_TARGET) $$($1_DEBUGINFO_FILES))
+	        $$($1_OBJCOPY) $(OBJCOPY_COMPRESS_FLAGS) --only-keep-debug $$($1_TARGET) $$($1_DEBUGINFO_FILES))
 	    $$(CHMOD) -x $$($1_DEBUGINFO_FILES)
           else ifeq ($(call isTargetOs, aix), true)
             # AIX does not provide the equivalent of objcopy to extract debug

src/hotspot/cpu/aarch64/aarch64.ad

@@ -1986,7 +1986,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
 
   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 
-  if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
+  if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
     assert((src_lo&1)==0 && src_lo+1==src_hi &&
            (dst_lo&1)==0 && dst_lo+1==dst_hi,
            "expected aligned-adjacent pairs");
@@ -2001,7 +2001,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
   int src_offset = ra_->reg2offset(src_lo);
   int dst_offset = ra_->reg2offset(dst_lo);
 
-  if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
+  if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
     uint ireg = ideal_reg();
     DEBUG_ONLY(int algm = MIN2(RegMask::num_registers(ireg), (int)Matcher::stack_alignment_in_slots()) * VMRegImpl::stack_slot_size);
     assert((src_lo_rc != rc_stack) || is_aligned(src_offset, algm), "unaligned vector spill sp offset %d (src)", src_offset);
@@ -2149,7 +2149,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
     } else {
       st->print("%s", Matcher::regName[dst_lo]);
     }
-    if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
+    if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
       int vsize = 0;
       switch (ideal_reg()) {
       case Op_VecD:

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -311,6 +311,12 @@ source %{
           return false;
         }
         break;
+      case Op_RotateLeftV:
+      case Op_RotateRightV:
+        if (length_in_bytes > 16) {
+          return false; // NEON only, since SLI/USHR are not available in SVE
+        }
+        break;
       default:
         break;
     }
@@ -370,6 +376,11 @@ source %{
       case Op_SqrtVHF:
       case Op_FmaVHF:
         return false;
+      // There's no SLI instruction in SVE, so we can't have an optimal vector
+      // rotate with masking when emitting code for SVE.
+      case Op_RotateLeftV:
+      case Op_RotateRightV:
+        return false;
       default:
         break;
     }
@@ -441,11 +452,11 @@ source %{
       // On architectures that do not support predicate, masks are stored in
       // general vector registers (TypeVect) with sizes ranging from TypeVectA
       // to TypeVectX based on the vector size in bytes.
-      assert(vt->isa_vectmask() == nullptr, "mask type is not matched");
+      assert(vt->isa_pvectmask() == nullptr, "mask type is not matched");
       return false;
     }
 
-    assert(vt->isa_vectmask() != nullptr, "expected TypeVectMask on SVE");
+    assert(vt->isa_pvectmask() != nullptr, "expected TypePVectMask on SVE");
     switch (opcode) {
       case Op_VectorMaskToLong:
       case Op_VectorLongToMask:
@@ -3229,6 +3240,25 @@ instruct vlsra_imm(vReg dst, vReg src, immI_positive shift) %{
   ins_pipe(pipe_slow);
 %}
 
+// vector rotate with constant shift count (NEON only)
+// Uses USHR+SLI 2-instruction sequence instead of SHL+USHR+ORR 3-instruction decomposition.
+
+instruct vrotateconstant(vReg dst, vReg src, immI shift) %{
+  predicate(Matcher::vector_length_in_bytes(n) <= 16);
+  match(Set dst (RotateLeftV src shift));
+  match(Set dst (RotateRightV src shift));
+  effect(TEMP_DEF dst);
+  format %{ "vrotateconstant $dst, $src, $shift" %}
+  ins_encode %{
+    int opc = this->ideal_Opcode();
+    int raw_shift = checked_cast<int>(opc == Op_RotateLeftV ?
+                                      $shift$$constant : -$shift$$constant);
+    __ neon_vector_rotate($dst$$FloatRegister, get_arrangement(this),
+                          $src$$FloatRegister, raw_shift);
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 // vector shift - predicated
 
 instruct vlsl_masked(vReg dst_src1, vReg src2, pRegGov pg) %{

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -301,6 +301,12 @@ source %{
           return false;
         }
         break;
+      case Op_RotateLeftV:
+      case Op_RotateRightV:
+        if (length_in_bytes > 16) {
+          return false; // NEON only, since SLI/USHR are not available in SVE
+        }
+        break;
       default:
         break;
     }
@@ -360,6 +366,11 @@ source %{
       case Op_SqrtVHF:
       case Op_FmaVHF:
         return false;
+      // There's no SLI instruction in SVE, so we can't have an optimal vector
+      // rotate with masking when emitting code for SVE.
+      case Op_RotateLeftV:
+      case Op_RotateRightV:
+        return false;
       default:
         break;
     }
@@ -431,11 +442,11 @@ source %{
       // On architectures that do not support predicate, masks are stored in
       // general vector registers (TypeVect) with sizes ranging from TypeVectA
       // to TypeVectX based on the vector size in bytes.
-      assert(vt->isa_vectmask() == nullptr, "mask type is not matched");
+      assert(vt->isa_pvectmask() == nullptr, "mask type is not matched");
       return false;
     }
 
-    assert(vt->isa_vectmask() != nullptr, "expected TypeVectMask on SVE");
+    assert(vt->isa_pvectmask() != nullptr, "expected TypePVectMask on SVE");
     switch (opcode) {
       case Op_VectorMaskToLong:
       case Op_VectorLongToMask:
@@ -1965,6 +1976,25 @@ instruct vlsra_imm(vReg dst, vReg src, immI_positive shift) %{
   ins_pipe(pipe_slow);
 %}
 
+// vector rotate with constant shift count (NEON only)
+// Uses USHR+SLI 2-instruction sequence instead of SHL+USHR+ORR 3-instruction decomposition.
+
+instruct vrotateconstant(vReg dst, vReg src, immI shift) %{
+  predicate(Matcher::vector_length_in_bytes(n) <= 16);
+  match(Set dst (RotateLeftV src shift));
+  match(Set dst (RotateRightV src shift));
+  effect(TEMP_DEF dst);
+  format %{ "vrotateconstant $dst, $src, $shift" %}
+  ins_encode %{
+    int opc = this->ideal_Opcode();
+    int raw_shift = checked_cast<int>(opc == Op_RotateLeftV ?
+                                      $shift$$constant : -$shift$$constant);
+    __ neon_vector_rotate($dst$$FloatRegister, get_arrangement(this),
+                          $src$$FloatRegister, raw_shift);
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 dnl
 dnl VSHIFT_PREDICATE($1,   $2,      $3  )
 dnl VSHIFT_PREDICATE(type, op_name, insn)

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -265,7 +265,7 @@ void C2_MacroAssembler::fast_lock(Register obj, Register box, Register t1,
       // Check if object matches.
       ldr(t3, Address(t1_monitor, ObjectMonitor::object_offset()));
       BarrierSetAssembler* bs_asm = BarrierSet::barrier_set()->barrier_set_assembler();
-      bs_asm->try_resolve_weak_handle_in_c2(this, t3, t2, slow_path);
+      bs_asm->try_peek_weak_handle_in_nmethod(this, t3, t3, t2, slow_path);
       cmp(t3, obj);
       br(Assembler::NE, slow_path);
 

src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp

@@ -393,6 +393,11 @@ void BarrierSetAssembler::check_oop(MacroAssembler* masm, Register obj, Register
   __ cbz(obj, error);      // if klass is null it is broken
 }
 
+void BarrierSetAssembler::try_peek_weak_handle_in_nmethod(MacroAssembler* masm, Register weak_handle, Register obj, Register tmp, Label& slow_path) {
+  // Load the oop from the weak handle without barriers.
+  __ ldr(obj, Address(weak_handle));
+}
+
 #ifdef COMPILER2
 
 OptoReg::Name BarrierSetAssembler::encode_float_vector_register_size(const Node* node, OptoReg::Name opto_reg) {
@@ -440,12 +445,6 @@ OptoReg::Name BarrierSetAssembler::refine_register(const Node* node, OptoReg::Na
 
   return opto_reg;
 }
-
-void BarrierSetAssembler::try_resolve_weak_handle_in_c2(MacroAssembler* masm, Register obj, Register tmp, Label& slow_path) {
-  // Load the oop from the weak handle.
-  __ ldr(obj, Address(obj));
-}
-
 #undef __
 #define __ _masm->
 

src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.hpp

@@ -130,12 +130,15 @@ class BarrierSetAssembler: public CHeapObj<mtGC> {
   static void clear_patching_epoch();
   static void increment_patching_epoch();
 
+  // See AS_NO_KEEPALIVE for peek semantics
+  // weak_handle and obj may alias
+  virtual void try_peek_weak_handle_in_nmethod(MacroAssembler* masm, Register weak_handle, Register obj, Register tmp, Label& slow_path);
+
 #ifdef COMPILER2
   OptoReg::Name encode_float_vector_register_size(const Node* node,
                                                   OptoReg::Name opto_reg);
   OptoReg::Name refine_register(const Node* node,
                                 OptoReg::Name opto_reg);
-  virtual void try_resolve_weak_handle_in_c2(MacroAssembler* masm, Register obj, Register tmp, Label& slow_path);
 #endif // COMPILER2
 };