tools/flash.sh: work around OpenOCD program-sector-0 bug on GD32F205#32
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Bench-confirmed 2026-05-24: OpenOCD 0.12.0 + stm32f1x driver targeting GD32F205 (CPUTAPID 0x1ba01477) silently fails to write flash sector 0 via the high-level `program` command. The "Verified OK" reports a false pass because verify_image uses the same broken loader path and reads back the same address-byte garbage (00 01 02 03 04 ...) that write produced. Chip then hard-faults on next reset trying to load the corrupted reset vector. Manual proof that hardware is fine: direct FLASH_KEYR unlock + PG/STRT write of a half-word at 0x08000000 lands correctly and reads back right. Silicon is healthy, only the OpenOCD loader-algorithm path is broken. Workaround: manual mass erase via direct FLASH_CR poking, then `flash write_image` + `verify_image` (lower-level path that doesn't use the broken loader). Tested on rippleon ROC001 — wall unit recovered from yesterday's busy_wait incident now boots cleanly. Also adds a post-flash message reminding the operator to power-cycle the unit before expecting the GFCI self-test to pass: the SWD halt during flash exceeds the external CCID chip's refresh-cycle watchdog window, latching the chip into fail-safe. Power cycle clears it. See feedback memory feedback-openocd-program-skips-sector0-gd32f205 for full detail + detection recipe. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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The bug
OpenOCD 0.12.0 +
stm32f1xdriver targeting GD32F205 (CPUTAPID 0x1ba01477)silently fails to write flash sector 0 via the high-level `program` command.
Symptoms:
`0x08000000: 03020100 07060504 0b0a0908 0f0e0d0c` — bytes 00 01 02 03 04...
Root cause (best guess): OpenOCD's stm32f1x loader algorithm has a subtle
interaction bug with the GD32F205 flash controller for sector 0. The verify
step uses the same broken path so the bug is invisible to OpenOCD.
Hardware verified healthy: manual unlock + direct flash controller poke
(KEY1/KEY2, set PG, half-word write, wait EOP) writes sector 0 correctly.
Only the loader-algorithm path is broken.
The fix
Replace the `program` invocation with:
sector-0 specific issue the loader has)
Also adds a post-flash reminder: after SWD flash, the external GFCI/CCID
chip is latched in fail-safe (MCU was halted >6 s during flash, exceeding
the chip's refresh watchdog). A power-cycle of the unit is required before
the boot self-test will pass. Documented in the post-flash message so
future operators don't lose time to it.
Cost
This bug + the GD32 PLL cache trap (separate finding) together cost ~12 hours
of debugging on 2026-05-24. After we noticed it, fix was 30 minutes. Saving
the next operator from the same trap.
Detection recipe
If you suspect this bit you on a previously-flashed unit:
```bash
openocd -f tools/openocd-gd32f205.cfg -c "init" -c "halt" \
-c "mdw 0x08000000 4" -c "shutdown"
```
If you see `03020100 07060504 0b0a0908 0f0e0d0c` — yep.
Test Plan
🤖 Generated with Claude Code