🚦 Traffic Light Controller (Verilog HDL)

This is my first digital design project in Verilog HDL: a Traffic Light Controller implemented and simulated using a testbench in ModelSim.

It simulates a simple traffic light system that controls the green, yellow, and red lights for three roads: G-light, R-light, and Y-light.

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🧠 Project Description

The Traffic Light Controller cycles through three traffic light phases:

• Green Light (glight): Vehicle passage allowed
• Yellow Light (ylight): Transition phase
• Red Light (rlight): Vehicle stop

Each phase is controlled using a finite state machine (FSM). A reset signal is used to restart the traffic light cycle.

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📁 Files Included

File	Description
Traffic_light_Controller.v	Main Verilog HDL module
Traffic_light_Controller.v.bak	Backup copy
README.md	Project documentation
*.png	Simulation waveform screenshots

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🧪 Simulation Screenshots

✅ Normal Operation

Displays state transitions from Green → Yellow → Red.

🔁 After Reset

FSM restarts after reset signal.

⏱ Clock and Light Timing

Shows exact timing of transitions.

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🔧 Tools Used

• Language: Verilog HDL
• Simulation: ModelSim by Mentor Graphics
• Editor: Vivado / VS Code / Pycharm (as preferred)

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🧰 How It Works

always @(posedge clk or posedge rst) begin
    if (rst) 
        state <= RESET_STATE;
    else 
        state <= next_state;
end