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Merged
YWHyuk merged 66 commits into from
Dec 1, 2025
Merged

Develop #188

YWHyuk merged 66 commits into from
Dec 1, 2025

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@YWHyuk
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@YWHyuk YWHyuk commented Dec 1, 2025

v1.0.1 update

  • Reimplement a MLIRMultiDim
  • Log stats fix, Rename ENV, and cleanup codes
  • Fix the incorrect interconnect frequency

YunSunny00 and others added 30 commits October 28, 2025 12:50
@YunSunny00
[docs] multi-tenancy load generator
38ebeeb
@YWHyuk
Improve README with multi-tenancy examples and details
ed18bb6 
Updated README to enhance clarity and provide code examples for multi-tenancy.
@YWHyuk
Merge pull request #172 from PSAL-POSTECH/readme
44b234e 
[Doc] Multi-tenant description update
@wok1909 @YWHyuk
[Frontend] Change ExecutionEngine to PyTorchSimExecutionEngine
0a6f248
@YWHyuk
[Refactor] Rename execution engine as a PyTorchSimRunner
216f4de
@YWHyuk
Merge pull request #168 from PSAL-POSTECH/tmp
6a0fcee 
[Frontend] Change ExecutionEngine to PyTorchSimExecutionEngine
@YWHyuk
[Refactor] Rearchitect MLIRMultiDim class
84b8b21
@YWHyuk
Merge pull request #174 from PSAL-POSTECH/Tile
5f9f098 
[Refactor] Rearchitect MLIRMultiDim class (WIP)
@YunSunny00 @YWHyuk
[Frontend] Template autotune
f10038e
@YWHyuk
[Cleanup] Remove codegen_headers
fe22e9b
@YWHyuk
[Cleanup] Refactor conv template + autotune primitive
f400d68
@YWHyuk
[Autotune] Connect autotune template
8c96a5a
@YWHyuk
[Fix] Fix wrong divder in reduction fusion
3692365
@YWHyuk
Merge pull request #167 from PSAL-POSTECH/autotune
4ed48b2 
[Frontend] Template autotune
@YWHyuk
[CI] Add accuracy validation
3660e2d
@YWHyuk
Merge pull request #178 from PSAL-POSTECH/accuracy
3b04ccf 
[CI] Add accuracy validation
@YWHyuk
[Fix] fix typo in backendsim + simlator.py (#176, #177)
1ed9ca6 
Reported-by: journewki
@YWHyuk
Merge pull request #180 from PSAL-POSTECH/typo
1ccc0db 
[Fix] fix typo in backendsim + simlator.py (#176, #177)
@YunSunny00
[doc] add CMEM in readme
9936bb0
@YunSunny00
[doc] autotune template readme
2eb2ea3
@YunSunny00
[environment] build from source
fd2bdc1 
handle #175 issue
@YWHyuk
Merge pull request #179 from PSAL-POSTECH/readme
1a5ad29 
Fix Readme & build script
@YWHyuk
[Performance] fix renamed variable access
ce9950f
@YWHyuk
[CI] Store validation results as an artifact
a6e6ea9
@YWHyuk
[Fix] Keep loop_size variable in the choice list
ca6a758
@YWHyuk
[Fix] Use correct vec_size #183
0fcc618
@YWHyuk
[CI] Use self-hosted runner for later stage of building
85a46a6
@YWHyuk
[Build] Remove deprecated submodule
0d306c5
@YWHyuk
[Cleanup] Remove deprecated llvm folders
3238d72
@YWHyuk
[CI] debug
18b769a
YWHyuk and others added 29 commits November 30, 2025 02:29
@YWHyuk
[Refactor] Rename *_log_print_interval_cycle -> *_stats_print_period_…
b9eaeff 
…cycles
@YWHyuk
[Refactor] Cleanup unused config options
ba600e8
@YWHyuk
[Refactor] Define trace log format: [cycle][core][event]
5bba4ae
@YWHyuk
Merge branch 'perf' into refactor
b96852a
@YWHyuk
Merge pull request #185 from PSAL-POSTECH/refactor
8ce1c5b 
Refactor
@YWHyuk
Merge branch 'develop' into perf
18daf42
@YWHyuk
[Fix] Change validation mode to functional mode
902f13a
@YWHyuk
[Fix] typo in interconnect logging message
2a0c0d7
@YWHyuk
Fix typo in core_stats_print_period_cycles
d62b12e
@YWHyuk
Fix path syntax for accuracy report artifact
8bcceaf
@wok1909
Change PyTorchSimBackend to TOGSim
623b7be
@YWHyuk
Merge pull request #186 from PSAL-POSTECH/rename
6675f59 
Change PyTorchSimBackend to TOGSim
@YunSunny00
[refactor] compiler opt config
e3cc1fb
@YunSunny00
[refactor] simulator log
10364c8
@YunSunny00
[Tutorial] HelloPyTorchSim
b220a90
@YWHyuk
Merge pull request #187 from PSAL-POSTECH/tutorial
853e93a 
Tutorial
@YWHyuk
[CI] remove deprecated file
184a83b
@YWHyuk
[Tutorial] Interface for Hands-on session
00f46ff
@wok1909
Dockerfile for tutorial
0d0e071
@wok1909
Fix method of getting param from os env
0d5745c
@YunSunny00 @wok1909
[Tutorial] fix env var
69b9b4b
@YunSunny00 @wok1909
[fix] log typo
3f5b50d
@YunSunny00 @wok1909
[fix] tutorial order fix
ef297f9
@wok1909
Add import math
0941856
@wok1909
Add session2 hands-on
31fec87
@YWHyuk
[TOGSim] Add VOQ for simple interconnect
a3ddabd
@YWHyuk
[TOGSim] Fix incorrect icnt frequency
a553288
@YWHyuk
[TOGSim] Fix DMA stat logging and unify stat formatting
66b0103
@YWHyuk
Merge pull request #181 from PSAL-POSTECH/perf
92aeeef 
Perf
@YWHyuk YWHyuk merged commit fd6d327 into master Dec 1, 2025
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4 participants

@YWHyuk @YunSunny00 @wok1909