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Make vPortYield weak in ARM_CRx_No_GIC port#1414

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maximdeclercq:main-arm-crx-weak
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Make vPortYield weak in ARM_CRx_No_GIC port#1414
maximdeclercq wants to merge 1 commit into
FreeRTOS:mainfrom
maximdeclercq:main-arm-crx-weak

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@maximdeclercq
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This change makes vPortYield a weak symbol so platforms with a dedicated software interrupt mechanism can substitute their own yield trigger by providing a strong vPortYield definition.

Default behaviour is unchanged. When no strong override is linked, the weak
default in portASM.S emits SVC 0 dispatched by FreeRTOS_SVC_Handler.

Test Steps

This patch has been tested using the ARM_CRx_No_GIC Example.

Checklist:

  • I have tested my changes. No regression in existing tests.
  • I have modified and/or added unit-tests to cover the code changes in this Pull Request.

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

Mark vPortYield as a weak symbol so chips with a dedicated software
interrupt register can substitute their own yield trigger.

Default behaviour is unchanged when no strong override is linked.

Signed-off-by: Maxim De Clercq <maximdeclercq00@gmail.com>
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sonarqubecloud Bot commented May 9, 2026

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codecov Bot commented May 22, 2026

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 91.37%. Comparing base (a8c9d35) to head (f7e264f).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files
@@           Coverage Diff           @@
##             main    #1414   +/-   ##
=======================================
  Coverage   91.37%   91.37%           
=======================================
  Files           6        6           
  Lines        3259     3259           
  Branches      902      902           
=======================================
  Hits         2978     2978           
  Misses        132      132           
  Partials      149      149           
Flag Coverage Δ
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2 participants