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Correct RISC-V port #endif preprocessor comments#1395

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patrzhan merged 1 commit intoFreeRTOS:mainfrom
cuiweixie:fix/riscv-port-endif-comment
Apr 3, 2026
Merged

Correct RISC-V port #endif preprocessor comments#1395
patrzhan merged 1 commit intoFreeRTOS:mainfrom
cuiweixie:fix/riscv-port-endif-comment

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Summary

Fix the #endif comment after vPortSetupTimerInterrupt in GCC and IAR RISC-V port.c: the comment duplicated configMTIME_BASE_ADDRESS and did not mention configMTIMECMP_BASE_ADDRESS, unlike the matching #if condition.

Files

  • portable/GCC/RISC-V/port.c
  • portable/IAR/RISC-V/port.c

This is a comment-only fix; preprocessor behavior is unchanged.

The comment after vPortSetupTimerInterrupt in GCC and IAR RISC-V port.c duplicated configMTIME_BASE_ADDRESS and omitted configMTIMECMP_BASE_ADDRESS. Align the comment with the matching #if condition.
@patrzhan patrzhan force-pushed the fix/riscv-port-endif-comment branch from d9ceebc to 03132e4 Compare April 3, 2026 21:42
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sonarqubecloud bot commented Apr 3, 2026

@patrzhan
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patrzhan commented Apr 3, 2026

Thank you for your contribution. The change looks good to me.

@patrzhan patrzhan merged commit 129b09f into FreeRTOS:main Apr 3, 2026
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3 participants