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1. Arcade-Game Arcade-Game Public

   Python

2. GavinBlackie/JavaFX-Chess-App GavinBlackie/JavaFX-Chess-App Public

   Java 2

3. Semi-RISC-CPU Semi-RISC-CPU Public

   This is the full implementation of a 32-Bit multi-cycle CPU in VHDL using Quartus and Modelsim for RTL design and simulation verification that will be emulated on the DE2-155 Altera FPGA Board

   VHDL 1

4. Pipelined-RV32I-RTL-to-GSDII Pipelined-RV32I-RTL-to-GSDII Public

   This project is about the implementation of a RV32I ISA based CPU in Verilog. This project's end goal is to start with a RTL Design to GDSII (Final File Format)

   Verilog 1

5. BookStore-App BookStore-App Public

   Java

6. HDL-Bits-Solutions HDL-Bits-Solutions Public

   This Repository purpose is to contain both the VDHL & Verilog solutions to the problems given in HDLBits website

   Verilog