Published in 34th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA' 2026)
Authors: Duc Hoang*, Aarush Gupta*, Philip Harris. MIT. *Equal Contributions.
We provided the environment in the environment.yml file, see Conda section for setting up. To activate the environment:
conda activate kancd benchmarks/<bench-mark-name>python train.pyWhere benchmark names could be JSC_CERNBox, or MNIST. This will generate the trained model saved in benchmarks/<bench-mark-name>/models
In the same benchmark directory:
python convert.pyEach of the convert file will have a model_tag parameter, if you do train a new model you have to modify it. Otherwise we provide the trained models as a baseline.
To run xsim with the generated RTL
cd models/<model-tag>/firmware/simTo check for correctness:
vivado -mode batch -source sim.tclTo measure latency:
vivado -mode batch -source sim_latency.tcl
To build the bit-file, or compile the project out of context
cd models/<model-tag>/firmware/vivado -mode batch -source vivado/build_full.tclor
vivado -mode batch -source vivado/build_ooc.tcl- Xilinx Virtex UltraScale+ FPGA:
xcvu9p-flgb2104-2-i - Zynq UltraScale+ MPSoC:
xczu7ev-ffvc1156-2-e - Vivado version:
2024.1
Create conda environment:
conda env create -f environment.yml -n kan
Activate the environment:
conda activate kan
And then do whatever you want in this environment (edit files, open notebooks, etc.). To deactivate the environment:
conda deactivate
If you make any update for the environment, please edit the environment.yml file and run:
conda env update --file environment.yml --prune
Reference on conda environment here: https://docs.conda.io/projects/conda/en/latest/user-guide/tasks/manage-environments.html

