B850 support part5

configs/config.msi_ms7e56

@@ -1,3 +1,4 @@
+CONFIG_OPTION_BACKEND_NONE=y
 CONFIG_VENDOR_MSI=y
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
 CONFIG_VGA_BIOS=y
@@ -10,21 +11,24 @@ CONFIG_VGA_BIOS_FILE="Phoenix_generic_vbios.bin"
 CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
 CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
 CONFIG_BOARD_MSI_PRO_B850_P=y
+CONFIG_TPM_MEASURED_BOOT=y
 CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp"
 CONFIG_PCIEXP_COMMON_CLOCK=y
 CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y
 CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE=y
-# CONFIG_ON_DEVICE_ROM_LOAD is not set
-CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y
-CONFIG_YABEL_DIRECTHW=y
+CONFIG_NO_GFX_INIT=y
 CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+CONFIG_DRIVERS_EFI_VARIABLE_STORE=y
+CONFIG_DRIVERS_EFI_FW_INFO=y
+CONFIG_TPM2=y
+# CONFIG_TPM_HASH_SHA1 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_PAYLOAD_EDK2=y
 CONFIG_EDK2_TAG_OR_REV="origin/cbmem_pci_rb_info"
-CONFIG_EDK2_DEBUG=y
+CONFIG_EDK2_CBMEM_LOGGING=y
 CONFIG_EDK2_LOAD_OPTION_ROMS=y
 # CONFIG_EDK2_PS2_SUPPORT is not set
-CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask=0x07"
+CONFIG_EDK2_SERIAL_SUPPORT=y
 CONFIG_EDK2_ENABLE_IPXE=y
 CONFIG_IPXE_ADD_SCRIPT=y
 CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe"
@@ -42,17 +46,16 @@ CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y
 CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y
 CONFIG_EDK2_DASHARO_POWER_CONFIG=y
 CONFIG_EDK2_DASHARO_PCI_CONFIG=y
-CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y
 CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y
 CONFIG_EDK2_BOOT_MENU_KEY=0x0015
 CONFIG_EDK2_SETUP_MENU_KEY=0x0008
 CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y
+CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y
 CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y
 CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y
 # CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS is not set
 # CONFIG_EDK2_FUM_AUTO_IPXE_BOOT is not set
 CONFIG_DISPLAY_MTRRS=y
 CONFIG_OPENSIL_DEBUG_PREFIX=y
 CONFIG_OPENSIL_DEBUG_APOB=y
-# CONFIG_OPENSIL_DEBUG_FCH is not set
 # CONFIG_OPENSIL_DEBUG_XUSL_CMN is not set

payloads/external/Makefile.mk

@@ -305,8 +305,11 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI)
 		CONFIG_EDK2_FW_VERSION=L"$(CONFIG_LOCALVERSION)" \
 		CONFIG_EDK2_FW_VENDOR=L"$(CONFIG_BIOS_VENDOR)" \
 		CONFIG_EDK2_FW_RELEASE_DATE=L"$(call get_build_value,COREBOOT_DMI_DATE)" \
-		CONFIG_EDK2_FW_REVISION=$(shell printf 0x"%04x%04x" $(DASHARO_MAJOR_VERSION) $(DASHARO_MINOR_VERSION))
-
+		CONFIG_EDK2_FW_REVISION=$(shell printf 0x"%04x%04x" $(DASHARO_MAJOR_VERSION) $(DASHARO_MINOR_VERSION)) \
+		CONFIG_EDK2_AMD_GOP_DRIVER=$(CONFIG_EDK2_AMD_GOP_DRIVER) \
+		CONFIG_EDK2_VGA_BIOS_VENDOR_ID=0x$(word 1,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \
+		CONFIG_EDK2_VGA_BIOS_DEVICE_ID=0x$(word 2,$(subst $(comma),$(spc),$(call strip_quotes,$(CONFIG_VGA_BIOS_ID)))) \
+		CONFIG_VGA_BIOS_FILE=$(CONFIG_VGA_BIOS_FILE)
 
 $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/edk2 UniversalPayload \

payloads/external/edk2/Kconfig

@@ -291,9 +291,17 @@ config EDK2_GOP_DRIVER
 	help
 	  Select this option to have edk2 use an external GOP driver for display init.
 
+config EDK2_AMD_GOP_DRIVER
+	bool "Add an AMD GOP driver to the Tianocore build"
+	depends on VGA_BIOS && NO_GFX_INIT && !EDK2_REPO_OFFICIAL && !EDK2_DISABLE_OPTION_ROMS
+	default y if VGA_BIOS && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX
+	help
+	  Select this option to have edk2 use an external GOP driver for AMD display init.
+
 config EDK2_GOP_FILE
 	string "GOP driver file"
-	depends on EDK2_GOP_DRIVER
+	depends on EDK2_GOP_DRIVER || EDK2_AMD_GOP_DRIVER
+	default "AmdGopDriver.efi" if EDK2_AMD_GOP_DRIVER
 	default "IntelGopDriver.efi"
 	help
 	  The name of the GOP driver file passed to edk2.

payloads/external/edk2/Makefile

@@ -462,6 +462,12 @@ endif
 ifneq ($(CONFIG_EDK2_FUM_AUTO_IPXE_BOOT),y)
 BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdFumAutoIpxeBoot=FALSE
 endif
+# USE_AMD_PLATFORM_GOP = FALSE
+ifeq ($(CONFIG_EDK2_AMD_GOP_DRIVER),y)
+BUILD_STR += -D USE_AMD_PLATFORM_GOP=TRUE
+BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomVendorId=$(CONFIG_EDK2_VGA_BIOS_VENDOR_ID)
+BUILD_STR += --pcd gDasharoPayloadPkgTokenSpaceGuid.AmdVbiosOptionRomDeviceId=$(CONFIG_EDK2_VGA_BIOS_DEVICE_ID)
+endif
 
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString=$(CONFIG_EDK2_FW_VERSION)
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor=$(CONFIG_EDK2_FW_VENDOR)
@@ -560,6 +566,11 @@ gop_driver: $(EDK2_PATH)
 		cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/IntelGopDriver.efi; \
 		cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/vbt.bin; \
 	fi; \
+	if [ -n "$(CONFIG_EDK2_AMD_GOP_DRIVER)" ]; then \
+		echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \
+		cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/AmdGopDriver.efi; \
+		cp $(top)/$(CONFIG_VGA_BIOS_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/Vbios.bin; \
+	fi; \
 
 lan_rom: $(EDK2_PATH)
 	case "$(CONFIG_EDK2_LAN_ROM_DRIVER)" in \

src/drivers/amd/promontory21/Kconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRIVERS_AMD_PROMONTORY21
+	bool
+	help
+	  Enable AMD Promontory21 chip driver.

src/drivers/amd/promontory21/Makefile.mk

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_AMD_PROMONTORY21) += chip.c

src/drivers/amd/promontory21/chip.c

@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_device.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <static.h>
+
+#include "chip.h"
+
+static const char *prom21_sata_acpi_name(const struct device *dev)
+{
+	return "STCR";
+}
+
+static const char *prom21_usp_acpi_name(const struct device *dev)
+{
+	return "UP00";
+}
+
+static const char *prom21_dsp_acpi_name(const struct device *dev)
+{
+	char *name;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return NULL;
+
+	name = malloc(ACPI_NAME_BUFFER_SIZE);
+	snprintf(name, ACPI_NAME_BUFFER_SIZE, "DP%02X", dev->path.pci.devfn);
+	name[4] = '\0';
+
+	return name;
+}
+
+struct device_operations prom21_sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.ops_pci		= &pci_dev_ops_pci,
+	.acpi_name		= prom21_sata_acpi_name,
+	.acpi_fill_ssdt		= acpi_device_write_pci_dev,
+};
+
+static struct pci_operations prom21_pcie_ops = {
+	.set_subsystem		= pci_dev_set_subsystem,
+};
+
+struct device_operations amd_prom21_usp_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.scan_bus		= pciexp_scan_bridge,
+	.reset_bus		= pci_bus_reset,
+	.acpi_name		= prom21_usp_acpi_name,
+	.acpi_fill_ssdt		= acpi_device_write_pci_dev,
+	.ops_pci		= &prom21_pcie_ops,
+};
+
+struct device_operations amd_prom21_dsp_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.scan_bus		= pciexp_scan_bridge,
+	.reset_bus		= pci_bus_reset,
+	.acpi_name		= prom21_dsp_acpi_name,
+	.acpi_fill_ssdt		= acpi_device_write_pci_dev,
+	.ops_pci		= &prom21_pcie_ops,
+};
+
+struct chip_operations drivers_amd_promontory21_ops = {
+	.name = "AMD Promontory21",
+};

src/drivers/amd/promontory21/chip.h

@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef PROMONTORY21_CHIP_H
+#define PROMONTORY21_CHIP_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <device/pci_def.h>
+
+#define PROM21_MAX_PCIE_LANES		12
+#define PROM21_MAX_PCIE_CLKREQ		6
+#define PROM21_MAX_SATA_PORTS		4
+#define PROM21_XHCI_MAX_USB3_PORTS	6
+#define PROM21_XHCI_MAX_USB2_PORTS	12
+
+#define PROM21_XHCI_DEVFN		PCI_DEVFN(0xc, 0)
+#define PROM21_SATA_DEVFN		PCI_DEVFN(0xd, 0)
+
+struct prom21_sata_phy {
+	bool    override;
+	uint8_t gen1_swing;
+	uint8_t gen2_swing;
+	uint8_t gen3_swing;
+	uint8_t gen1_emp_level;
+	uint8_t gen2_emp_level;
+	uint8_t gen3_emp_level;
+};
+
+struct prom21_usb3_phy {
+	bool    override;
+	uint8_t gen1_swing;
+	uint8_t gen1_emp_level_en;
+	uint8_t gen1_emp_level;
+	uint8_t gen1_preshoot_en;
+	uint8_t gen1_preshoot;
+	uint8_t gen2_swing;
+	uint8_t gen2_cp0_emp_level_en;
+	uint8_t gen2_cp0_emp_level;
+	uint8_t gen2_cp0_preshoot_en;
+	uint8_t gen2_cp0_preshoot;
+	uint8_t gen2_cp13_emp_level_en;
+	uint8_t gen2_cp13_emp_level;
+	uint8_t gen2_cp13_preshoot_en;
+	uint8_t gen2_cp13_preshoot;
+	uint8_t gen2_cp14_emp_level_en;
+	uint8_t gen2_cp14_emp_level;
+	uint8_t gen2_cp14_preshoot_en;
+	uint8_t gen2_cp14_preshoot;
+	uint8_t gen2_cp15_emp_level_en;
+	uint8_t gen2_cp15_emp_level;
+	uint8_t gen2_cp15_preshoot_en;
+	uint8_t gen2_cp15_preshoot;
+	uint8_t gen2_cp16_emp_level_en;
+	uint8_t gen2_cp16_emp_level;
+	uint8_t gen2_cp16_preshoot_en;
+	uint8_t gen2_cp16_preshoot;
+};
+
+struct prom21_usb2_phy {
+	bool    override;
+	uint8_t slew_rate;
+	uint8_t driving_current;
+	uint8_t termination;
+};
+
+enum prom21_xhci_port_gen {
+	XhciPortGenDefault = 0,
+	XhciPortGen1 = 1,
+	XhciPortGen2 = 2
+};
+
+enum prom21_xhci_gen {
+	XhciGenDefault = 0,
+	XhciGen2x2 = 1,
+	XhciGen2x1 = 2
+};
+
+enum prom21_boolean {
+	HwDefault = 0,
+	Disable = 1,
+	Enable = 2
+};
+
+enum prom21_sata_mode {
+	SataAhci = 0,
+	SataRAID = 1
+};
+
+enum prom21_clkreq_pin_select {
+	ClkreqPort0,
+	ClkreqPort1,
+	ClkreqPort2,
+	ClkreqPort3,
+	ClkreqPort4,
+	ClkreqPort5,
+	ClkreqPort6,
+	ClkreqPort7,
+	ClkreqPort8,
+	ClkreqPort9,
+	ClkreqPort10,
+	ClkreqPort11,
+	ClkreqUnused = 0xe
+};
+
+enum prom21_clkreq_mode {
+	ClkreqMode,
+	ClkAlwaysOn,
+	ClkAlwaysOff,
+	GpioMode
+};
+
+struct prom21_sata_config {
+	enum prom21_sata_mode sata_mode;
+	enum prom21_boolean aggresive_link_pm_cap;
+	enum prom21_boolean psc_cap;
+	enum prom21_boolean ssc_cap;
+	enum prom21_boolean hot_plug;
+	enum prom21_boolean cccs_cap;
+	enum prom21_boolean msi_cap;
+	uint8_t port_enable[PROM21_MAX_SATA_PORTS];
+	enum prom21_boolean aggressive_dev_slp[PROM21_MAX_SATA_PORTS];
+};
+
+struct prom21_usb_config {
+	enum prom21_xhci_gen usb3_gen;
+	enum prom21_xhci_port_gen port_gen[PROM21_XHCI_MAX_USB3_PORTS];
+	enum prom21_boolean hw_lpm;
+	enum prom21_boolean dbc;
+};
+
+struct prom21_pcie_config {
+	enum prom21_boolean report_small_ltr;
+	bool gen1_swing_enable;
+	uint8_t pcie_gen1_swing[PROM21_MAX_PCIE_LANES];
+	uint8_t eq_preset;
+	bool gpio_perst_enable;
+	enum prom21_boolean msi;
+	enum prom21_boolean msix;
+	enum prom21_clkreq_pin_select clkreq_pin_select[PROM21_MAX_PCIE_CLKREQ];
+	enum prom21_clkreq_mode clkreq_mode[PROM21_MAX_PCIE_CLKREQ];
+	enum prom21_boolean lane_reversal_en[PROM21_MAX_PCIE_LANES / 2];
+	uint8_t port_target_speed[PROM21_MAX_PCIE_LANES];
+};
+
+struct drivers_amd_promontory21_config {
+	enum prom21_boolean si_prog_enable;
+	struct prom21_usb3_phy usb3_phy[PROM21_XHCI_MAX_USB3_PORTS];
+	struct prom21_usb2_phy usb2_phy[PROM21_XHCI_MAX_USB2_PORTS];
+	struct prom21_sata_phy sata_phy[PROM21_MAX_SATA_PORTS];
+
+	struct prom21_usb_config usb;
+	struct prom21_sata_config sata;
+	struct prom21_pcie_config pcie;
+};
+
+#endif /* OPENSIL_PHOENIX_POC_MPIO_CHIP_H */