CFS Aligner Design & Verification

A robust SystemVerilog implementation of a configurable Data Aligner module, accompanied by a comprehensive UVM (Universal Verification Methodology) testbench.

📖 Overview

The CFS Aligner is a hardware module designed to align streaming data based on offset and size parameters. It bridges a data producer and consumer, managing data alignment, buffering, and flow control. The project includes a full verification environment to ensure functional correctness across various configurations.

Motivation

In high-speed data processing pipelines, data often arrives unaligned or in varying chunk sizes. This module solves the problem of re-aligning valid data segments for downstream processing, providing a standard interface for control (APB) and data streaming (MD protocol).

✨ Key Features

Configurable Design: Parameterizable Data Width (ALGN_DATA_WIDTH) and FIFO Depth (FIFO_DEPTH).
Standard Control Interface: APB (Advanced Peripheral Bus) Slave interface for configuration and status registers.
Streaming Data Interface: Custom "MD" (Metadata/Media Data) protocol for RX (Input) and TX (Output) with valid/ready flow control.
Interrupt Support: Integrated interrupt logic for status reporting.
UVM Verification:
- Modular UVM Environment (Env, Agents, Scoreboard, Predictor).
- Reusable VIPs (Verification IPs) for APB and MD protocols.
- Functional Coverage and Register Model (RAL).

🛠 Tech Stack

Language: SystemVerilog (IEEE 1800)
Methodology: UVM (Universal Verification Methodology)
Tools: Compatible with standard EDA simulators (QuestaSim, VCS, Xcelium, Vivado Simulator).

📂 Project Structure

The repository is organized as follows:

Design (RTL):
- cfs_aligner.v: Top-level wrapper.
- cfs_aligner_core.v: Core alignment logic.
- cfs_synch_fifo.v: Synchronization FIFO.
- cfs_*_ctrl.v: Control logic modules.
Verification (UVM):
- cfs_algn_env.sv: Top-level UVM Environment.
- cfs_apb_agent/: APB Verification IP (Driver, Monitor, Sequencer).
- cfs_md_agent/: MD Protocol Verification IP.
- cfs_algn_reg_block.sv: Register Abstraction Layer (RAL) model.
- cfs_algn_scoreboard.sv: Data integrity checker.
- cfs_algn_coverage.sv: Functional coverage collector.
Simulation:
- testbench.sv: Top-level testbench module.
- messages.f: Compilation file list.

🚀 Installation & Setup

Clone the repository:

git clone https://github.com/your-username/cfs-aligner-verification.git
cd cfs-aligner-verification

Prerequisites:
- A SystemVerilog simulator (e.g., Siemens QuestaSim, Synopsys VCS, Cadence Xcelium).
- UVM 1.1d or 1.2 library compiled for your simulator.

🏃 Usage

To run a simulation, you need to compile the design and testbench files listed in messages.f and execute the simulation with a specific UVM test name.

Generic Simulation Steps

Compile:

# Example for QuestaSim
vlog -sv +incdir+. -f messages.f

Simulate:

# Example for QuestaSim
vsim -c testbench -do "run -all" +UVM_TESTNAME=cfs_algn_test_random

Available Tests

The following UVM tests are defined in cfs_algn_test_pkg.sv:

Test Name	Description
`cfs_algn_test_reg_access`	Verifies Read/Write access to APB registers (CSRs).
`cfs_algn_test_random`	Randomized data traffic on RX/TX with random configurations.
`cfs_algn_test_random_rx_err`	Injects errors on the RX interface to verify robustness.
`cfs_algn_test_base`	Base test for sanity checks and environment bring-up.

⚙️ Configuration

The cfs_aligner module can be configured via Verilog parameters:

module cfs_aligner#(
  parameter ALGN_DATA_WIDTH = 32, // Width of the data bus
  parameter FIFO_DEPTH      = 8   // Depth of the internal buffering
) ...

🧪 Testing Strategy

The verification environment uses a Scoreboard (cfs_algn_scoreboard) to compare the DUT output against a reference Model (cfs_algn_model).

Data Path: Verified by sending random packets via md_rx_agent and checking integrity at md_tx_agent.
Control Path: Verified via apb_agent performing Register Reads/Writes.
Coverage: cfs_algn_coverage tracks functional coverage points to ensure all scenarios (FIFO full/empty, backpressure, interrupts) are exercised.

🔮 Roadmap / Future Work

Add Clock Domain Crossing (CDC) support (currently placeholders CDC_RX_TO_REG, CDC_REG_TO_TX exist).
Expand coverage metrics.
Add formal verification properties (SVA).
Provide a Makefile for automated regression running.

🤝 Contributing

Contributions are welcome! Please follow these steps:

Fork the project.
Create your feature branch (git checkout -b feature/AmazingFeature).
Commit your changes (git commit -m 'Add some AmazingFeature').
Push to the branch (git push origin feature/AmazingFeature).
Open a Pull Request.

🎓 Acknowledgements

This project was developed as part of a Design Verification with SystemVerilog & UVM course on Udemy.

Original Author / Instructor: Cristian Florin Slav
Course: Design Verification with SystemVerilog

While the core logic and architecture follow the course material, this repository serves as a personal implementation and study reference to demonstrate proficiency in UVM environments, agent development, and functional coverage.

Name		Name	Last commit message	Last commit date
Latest commit History 37 Commits
README.md		README.md
cfs_algn_clr_cnt_drop.sv		cfs_algn_clr_cnt_drop.sv
cfs_algn_coverage.sv		cfs_algn_coverage.sv
cfs_algn_env.sv		cfs_algn_env.sv
cfs_algn_env_config.sv		cfs_algn_env_config.sv
cfs_algn_if.sv		cfs_algn_if.sv
cfs_algn_model.sv		cfs_algn_model.sv
cfs_algn_pkg.sv		cfs_algn_pkg.sv
cfs_algn_reg_access_status_info.sv		cfs_algn_reg_access_status_info.sv
cfs_algn_reg_block.sv		cfs_algn_reg_block.sv
cfs_algn_reg_ctrl.sv		cfs_algn_reg_ctrl.sv
cfs_algn_reg_irq.sv		cfs_algn_reg_irq.sv
cfs_algn_reg_irqen.sv		cfs_algn_reg_irqen.sv
cfs_algn_reg_pkg.sv		cfs_algn_reg_pkg.sv
cfs_algn_reg_predictor.sv		cfs_algn_reg_predictor.sv
cfs_algn_reg_status.sv		cfs_algn_reg_status.sv
cfs_algn_scoreboard.sv		cfs_algn_scoreboard.sv
cfs_algn_seq_reg_config.sv		cfs_algn_seq_reg_config.sv
cfs_algn_split_info.sv		cfs_algn_split_info.sv
cfs_algn_test_base.sv		cfs_algn_test_base.sv
cfs_algn_test_defines.sv		cfs_algn_test_defines.sv
cfs_algn_test_pkg.sv		cfs_algn_test_pkg.sv
cfs_algn_test_random.sv		cfs_algn_test_random.sv
cfs_algn_test_random_rx_err.sv		cfs_algn_test_random_rx_err.sv
cfs_algn_test_reg_access.sv		cfs_algn_test_reg_access.sv
cfs_algn_types.sv		cfs_algn_types.sv
cfs_algn_virtual_sequence_base.sv		cfs_algn_virtual_sequence_base.sv
cfs_algn_virtual_sequence_reg_access_random.sv		cfs_algn_virtual_sequence_reg_access_random.sv
cfs_algn_virtual_sequence_reg_access_unmapped.sv		cfs_algn_virtual_sequence_reg_access_unmapped.sv
cfs_algn_virtual_sequence_reg_config.sv		cfs_algn_virtual_sequence_reg_config.sv
cfs_algn_virtual_sequence_reg_status.sv		cfs_algn_virtual_sequence_reg_status.sv
cfs_algn_virtual_sequence_rx.sv		cfs_algn_virtual_sequence_rx.sv
cfs_algn_virtual_sequence_rx_err.sv		cfs_algn_virtual_sequence_rx_err.sv
cfs_algn_virtual_sequence_slow_pace.sv		cfs_algn_virtual_sequence_slow_pace.sv
cfs_algn_virtual_sequencer.sv		cfs_algn_virtual_sequencer.sv
cfs_aligner.v		cfs_aligner.v
cfs_aligner_core.v		cfs_aligner_core.v
cfs_apb_agent.sv		cfs_apb_agent.sv
cfs_apb_agent_config.sv		cfs_apb_agent_config.sv
cfs_apb_coverage.sv		cfs_apb_coverage.sv
cfs_apb_driver.sv		cfs_apb_driver.sv
cfs_apb_if.sv		cfs_apb_if.sv
cfs_apb_item_base.sv		cfs_apb_item_base.sv
cfs_apb_item_drv.sv		cfs_apb_item_drv.sv
cfs_apb_item_mon.sv		cfs_apb_item_mon.sv
cfs_apb_monitor.sv		cfs_apb_monitor.sv
cfs_apb_pkg.sv		cfs_apb_pkg.sv
cfs_apb_reg_adapter.sv		cfs_apb_reg_adapter.sv
cfs_apb_sequence_base.sv		cfs_apb_sequence_base.sv
cfs_apb_sequence_random.sv		cfs_apb_sequence_random.sv
cfs_apb_sequence_rw.sv		cfs_apb_sequence_rw.sv
cfs_apb_sequence_simple.sv		cfs_apb_sequence_simple.sv
cfs_apb_types.sv		cfs_apb_types.sv
cfs_ctrl.v		cfs_ctrl.v
cfs_edge_detect.v		cfs_edge_detect.v
cfs_md_agent.sv		cfs_md_agent.sv
cfs_md_agent_config.sv		cfs_md_agent_config.sv
cfs_md_agent_config_master.sv		cfs_md_agent_config_master.sv
cfs_md_agent_config_slave.sv		cfs_md_agent_config_slave.sv
cfs_md_agent_master.sv		cfs_md_agent_master.sv
cfs_md_agent_slave.sv		cfs_md_agent_slave.sv
cfs_md_coverage.sv		cfs_md_coverage.sv
cfs_md_driver.sv		cfs_md_driver.sv
cfs_md_driver_master.sv		cfs_md_driver_master.sv
cfs_md_driver_slave.sv		cfs_md_driver_slave.sv
cfs_md_if.sv		cfs_md_if.sv
cfs_md_item_base.sv		cfs_md_item_base.sv
cfs_md_item_drv.sv		cfs_md_item_drv.sv
cfs_md_item_drv_master.sv		cfs_md_item_drv_master.sv
cfs_md_item_drv_slave.sv		cfs_md_item_drv_slave.sv
cfs_md_item_mon.sv		cfs_md_item_mon.sv
cfs_md_monitor.sv		cfs_md_monitor.sv
cfs_md_pkg.sv		cfs_md_pkg.sv
cfs_md_sequence_base.sv		cfs_md_sequence_base.sv
cfs_md_sequence_base_master.sv		cfs_md_sequence_base_master.sv
cfs_md_sequence_base_slave.sv		cfs_md_sequence_base_slave.sv
cfs_md_sequence_simple_master.sv		cfs_md_sequence_simple_master.sv
cfs_md_sequence_simple_slave.sv		cfs_md_sequence_simple_slave.sv
cfs_md_sequence_slave_response.sv		cfs_md_sequence_slave_response.sv
cfs_md_sequence_slave_response_forever.sv		cfs_md_sequence_slave_response_forever.sv
cfs_md_sequencer_base.sv		cfs_md_sequencer_base.sv
cfs_md_sequencer_base_master.sv		cfs_md_sequencer_base_master.sv
cfs_md_sequencer_base_slave.sv		cfs_md_sequencer_base_slave.sv
cfs_md_sequencer_master.sv		cfs_md_sequencer_master.sv
cfs_md_sequencer_slave.sv		cfs_md_sequencer_slave.sv
cfs_md_types.sv		cfs_md_types.sv
cfs_regs.v		cfs_regs.v
cfs_rx_ctrl.v		cfs_rx_ctrl.v
cfs_synch.v		cfs_synch.v
cfs_synch_fifo.v		cfs_synch_fifo.v
cfs_tx_ctrl.v		cfs_tx_ctrl.v
design.sv		design.sv
messages.f		messages.f
testbench.sv		testbench.sv
uvm_ext_agent.sv		uvm_ext_agent.sv
uvm_ext_agent_config.sv		uvm_ext_agent_config.sv
uvm_ext_coverage.sv		uvm_ext_coverage.sv
uvm_ext_driver.sv		uvm_ext_driver.sv
uvm_ext_monitor.sv		uvm_ext_monitor.sv
uvm_ext_pkg.sv		uvm_ext_pkg.sv

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CFS Aligner Design & Verification

📖 Overview

Motivation

✨ Key Features

🛠 Tech Stack

📂 Project Structure

🚀 Installation & Setup

🏃 Usage

Generic Simulation Steps

Available Tests

⚙️ Configuration

🧪 Testing Strategy

🔮 Roadmap / Future Work

🤝 Contributing

🎓 Acknowledgements

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CFS Aligner Design & Verification

📖 Overview

Motivation

✨ Key Features

🛠 Tech Stack

📂 Project Structure

🚀 Installation & Setup

🏃 Usage

Generic Simulation Steps

Available Tests

⚙️ Configuration

🧪 Testing Strategy

🔮 Roadmap / Future Work

🤝 Contributing

🎓 Acknowledgements

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