Document NI TTL channel mapping on the DA_Ephys page#2703
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| data channels used by MIES. | ||
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| MIES uses PFI pins internally for timing and triggering tasks, for example | ||
| acquisition start triggers during pressure control. Users should not connect |
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@copilot we actually use these TTL signals to control solenoid valves used for pressure regulation. They control pressure access to the pipette tip between the user, the pressure regulator, and atmosphere.
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Thanks for the correction. Updated in 8d2a72e: the overview now describes pipette pressure regulation (switching the tip between user-applied pressure, the pressure regulator, and atmosphere) as a typical use of these TTL outputs, and I removed the inaccurate "acquisition start triggers during pressure control" example from the PFI section so it no longer implies pressure control runs over PFI.
Rendered preview of the updated section:
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Just as a heads up, I was blocked by some firewall rules while working on your feedback. Expand below for details. Warning Firewall rules blocked me from connecting to one or more addresses (expand for details)I tried to connect to the following addresses, but was blocked by firewall rules:
If you need me to access, download, or install something from one of these locations, you can either:
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| MIES supports up to 8 TTL output channels on NI DAC devices. On NI hardware | ||
| these TTL channels are delivered through Digital I/O (DIO) Port 0. | ||
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| A typical use of these TTL outputs is to control solenoid valves for pipette |
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@copilot This applies to PFI pins, not MIES TTL / Port 0 pins.
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Got it — fixed in a09da43. The solenoid valve / pipette pressure regulation description is no longer in the Port 0 overview at the top of the page; it is now described in the PFI pins section, where it correctly applies.
Rendered preview of the updated page:
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Just as a heads up, I was blocked by some firewall rules while working on your feedback. Expand below for details. Warning Firewall rules blocked me from connecting to one or more addresses (expand for details)I tried to connect to the following addresses, but was blocked by firewall rules:
If you need me to access, download, or install something from one of these locations, you can either:
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Pull request overview
Adds NI-specific DA_Ephys user documentation describing how MIES maps TTL output channels to NI DAQmx DIO Port 0 lines, and integrates that content into the rendered daephys.html page while avoiding Sphinx duplicate-label issues from standalone discovery.
Changes:
- Added a new included documentation fragment describing TTL0–TTL7 ↔
/{DeviceName}/port0/line0..7(P0.0..P0.7) and related NI hardware notes. - Included the new TTL documentation section at the end of
daephys.rstso it renders under the DA_Ephys page. - Updated Sphinx
exclude_patternsto prevent the include-only fragment from being built/discovered as a standalone source file.
Reviewed changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 1 comment.
| File | Description |
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| Packages/doc/daephys.rst | Includes the new NI TTL mapping documentation fragment into the DA_Ephys page. |
| Packages/doc/daephys_ttl_ni.rst | New NI TTL mapping and usage documentation (TTL vs PFI explanation, enabling steps, hardware notes). |
| Packages/doc/conf.py | Excludes the include-only fragment from Sphinx source discovery to avoid duplicate-label issues. |
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@copilot I added the appropriate URLs or hosts to the custom allowlist in this repository. |
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@copilot can you share the markdown rendering of the new documentation in this conversation? |
Sure — here is the new documentation rendered as Markdown (source is TTL channels on NI DAC devicesMIES supports up to 8 TTL output channels on NI DAC devices. On NI hardware these TTL channels are delivered through Digital I/O (DIO) Port 0. Physical connectionsThe mapping between MIES TTL channel numbers, NI DAQmx channel names, and the connector labels used on NI hardware is:
PFI pinsNI devices also provide PFI (Programmable Function Interface) pins such as MIES utilizes PFI pins internally to manage timing and triggering tasks. These pins serve as control lines for actuating solenoid valves that regulate pipette pressure, enabling switching of the pipette tip between user-applied pressure, the pressure regulator, and atmospheric pressure. MIES also uses PFI pins to synchronize data acquisition across multiple NI boards. For example, two NI PCIe-6343 boards can be combined to obtain 8 analog output channels by sharing start triggers and the sample clock over PFI lines. The Enabling TTL channels in MIESTo enable TTL output channels in MIES:
Hardware notes
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| data channels exposed by MIES on Port 0. | ||
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| MIES utilizes PFI pins internally to manage timing and triggering tasks. | ||
| These pins serve as control lines for actuating solenoid valves that regulate |
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@copilot lines 62, 63 and 64 should be moved to a new section that describes the use of TTL channels for pressure control.
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Done in 1f9149d. Moved the solenoid valve / pipette pressure description out of the PFI section into a new "Pipette pressure control" section under the TTL channels (Port 0) content.
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@MichaelHuth this link should work |
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| MIES utilizes PFI pins internally to manage timing and triggering tasks. | ||
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| MIES also uses PFI pins to synchronize data acquisition across multiple NI |
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@copilot This should read: "Specifically, MIES uses PFI pins to......"
it should be in the same paragraph as line 61.
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Done in e04cc06. Merged the multi-board sync sentence into the same paragraph as line 61, starting with "Specifically, MIES uses PFI pins to...".
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Thanks for opening a PR in MIES ✨!
here for the detailed explanation.
This PR adds DA_Ephys user documentation for how MIES maps NI TTL outputs to DIO Port 0, describes how those TTL channels are used for pipette pressure control, and clarifies the role of PFI pins (internal timing/triggering and multi-board acquisition synchronization) versus Port 0 (MIES TTL output channels).
User docs
Packages/doc/daephys_ttl_ni.rst/{DeviceName}/port0/line0..7andP0.0..P0.7HARDWARE_NI_TTL_PORT = 0P0.xpins are the MIES TTL output channels controlled from the DA_Ephys TTL tabDA_Ephys page integration
Packages/doc/daephys.rstso it renders underdaephys.htmlSphinx source layout
Packages/doc/conf.pyto avoid duplicate label generationOriginal prompt
Goal
Add a new user documentation section explaining how MIES uses TTL channels on NI DAC devices. This section should appear under the DA_Ephys documentation page at
https://alleninstitute.github.io/MIES/daephys.html.Background
The documentation is built with Sphinx from
.rstfiles inPackages/doc/. The main DA_Ephys page isPackages/doc/daephys.rst. Existing patterns in the repo (e.g.databrowser_artefactremoval.rst,databrowser_channelselection.rst) show that sub-topics are written as small standalone.rstfiles that are included with.. include::directives in the parent page.What to do
1. Create a new file
Packages/doc/daephys_ttl_ni.rstWrite it in reStructuredText following the style of the existing documentation in this repo. The content should cover:
Overview: MIES supports up to 8 TTL output channels on NI DAC devices, delivered via Digital I/O (DIO) Port 0.
Physical connections: A table mapping MIES TTL channel numbers (TTL0–TTL7) to NI DAQmx channel names (
/{DeviceName}/port0/line0…line7) and physical connector labels (P0.0…P0.7). Include notes that:{DeviceName}is the NI-assigned device name as shown in NI MAX (e.g.Dev1).HARDWARE_NI_TTL_PORT = 0) — this is fixed in the source code and cannot be changed from the GUI.PFI pins: Explain that NI devices also expose PFI (Programmable Function Interface) pins (e.g. PFI0, PFI1 …). These are digital lines but are not the TTL data channels used by MIES. PFI pins are used internally by MIES for timing and triggering (e.g. acquisition start triggers during pressure control). Users should not connect experimental TTL signals to PFI pins; use the P0.x pins instead.
Enabling TTL channels in MIES: Brief steps — open the DA_Ephys panel, go to the TTL tab, check the channel, select a stimulus set from the drop-down.
Hardware notes:
Use a Sphinx label
.. _daephys_ttl_ni:at the top of the file so it can be cross-referenced.2. Edit
Packages/doc/daephys.rstAppend an
.. include:: daephys_ttl_ni.rstdirective at the end of the file to pull the new content into the DA_Ephys page.Reference information (verified from source code)
HARDWARE_NI_TTL_PORT = 0— defined inPackages/MIES/MIES_Constants.ipf"/" + deviceName + "/port" + num2str(HARDWARE_NI_TTL_PORT) + "/line" + num2str(channelNumber)— fromPackages/MIES/MIES_DAC-Hardware.ipfpfi0andpfi1used as trigger inputs for DAQmx_Scan and DAQmx_WaveformGen — fromPackages/MIES/MIES_PressureControl.ipfChannelNumbercolumn of DAQConfigWave — fromPackages/MIES/MIES_WaveDataFolderGetters.ipfandPackages/MIES/MIES_DataConfigurator.ipfExisting file to modify
Packages/doc/daephys.rstcurrently ends at line 60 with:Add the include directive after this last line.
The following is the prior conversation context from the user's chat exploration (may be truncated):
User: In MIES, when using an NI DAC, what are the NI channel names that correspond to TTL0?
Assistant: The answer is found directly in the hardware preparation code in
MIES_DAC-Hardware.ipfand the constant definition inMIES_Constants.ipf.TTL0 on an NI DAC maps to the channel name:
/{DeviceName}/port0/line0Here's how it's constructed:
The port is always fixed to
HARDWARE_NI_TTL_PORT = 0: