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ITS3: ITS3 Digitisation Development after TDR #14145

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Merged
mconcas merged 4 commits into from
May 6, 2025
Merged

ITS3: ITS3 Digitisation Development after TDR #14145

mconcas merged 4 commits into from
May 6, 2025

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@ChunzhengLab
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@ChunzhengLab ChunzhengLab commented Apr 4, 2025 •
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  • The ITS3 inner barrel now supports multiple types of chip response inputs (currently ALPIDE and APTS, with support for MOSIAX coming soon).
  • The inner and outer barrels now support independent topology dictionaries.
  • Fixed several bugs.

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github-actions bot commented Apr 4, 2025

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@alibuild alibuild mentioned this pull request Apr 4, 2025
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f3sch commented Apr 4, 2025

Excellent @ChunzhengLab, thanks!
Just to give a bit of context and not to scare people this branch currently includes everything from #13894, #13895, #14137 and will be rebased afterward only leaving changes in ITS3.

@ChunzhengLab ChunzhengLab force-pushed the digi_its3 branch 2 times, most recently from 255c9ac to 493227a Compare April 7, 2025 08:21
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ChunzhengLab commented Apr 7, 2025

I’ve rebased the branch onto dev and grouped the commits logically. @f3sch

@ChunzhengLab ChunzhengLab force-pushed the digi_its3 branch 2 times, most recently from f7a299f to 6dc1bd2 Compare April 9, 2025 06:19
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f3sch commented Apr 12, 2025

Hi @ChunzhengLab, looking at the diff there are some artefacts left from my PR leading to merge conflicts now.

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f3sch requested changes Apr 14, 2025
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Nice work, I left some comments.

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ChunzhengLab commented Apr 16, 2025 •
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Thanks for the very good comments @f3sch. Please let me know any further suggestions.

@ChunzhengLab
ITS3 digitization: parameters, segmentation and container fixes
1350fb3 
- Add digitization parameter sets
- Fix C2F/F2C conversion in SegmentationMosaix
- Set scale function for Alpide as IB
- Fix chip digits container initialization
- Correct ordering of maxRows and maxCols
- Add support for floating row/column numbers in D2L
@ChunzhengLab
Introduce ChipSimResponse with response-centre extraction logic
f8a5657 
Add more info in CreateDic macro
@ChunzhengLab
Add a macro to compare ITS3 clusters and digits on a pixel array
ef99c60 
Add the script to check hits and clusters on a track

Add script for visualizing chip responses
@alibuild alibuild mentioned this pull request Apr 21, 2025
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f3sch reviewed Apr 22, 2025
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nice, just left one nitpick otherwise I think it is ready to updraft. for others to review

@ChunzhengLab ChunzhengLab marked this pull request as ready for review April 22, 2025 15:50
@ChunzhengLab ChunzhengLab requested a review from f3sch April 22, 2025 15:51
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alibuild commented Apr 26, 2025 •
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Error while checking build/O2/fullCI_slc9 for 1c10051 at 2025-05-05 22:05:

## sw/BUILD/o2checkcode-latest/log
--
========== List of errors found ==========
++ GRERR=0
++ grep -v clang-diagnostic-error error-log.txt
++ grep ' error:'
/sw/SOURCES/O2/14145-slc9_x86-64/0/Detectors/Upgrades/ITS3/simulation/src/ChipDigitsContainer.cxx:51:65: error: statement should be inside braces [readability-braces-around-statements]
/sw/SOURCES/O2/14145-slc9_x86-64/0/Detectors/Upgrades/ITS3/simulation/src/ChipDigitsContainer.cxx:53:71: error: statement should be inside braces [readability-braces-around-statements]
/sw/SOURCES/O2/14145-slc9_x86-64/0/Detectors/Upgrades/ITS3/simulation/src/ChipDigitsContainer.cxx:56:27: error: statement should be inside braces [readability-braces-around-statements]
++ [[ 0 == 0 ]]
++ exit 1
--

Full log here.

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fgrosa commented May 6, 2025

@fprino @mconcas could you please check if the changes for the ITS part are fine? They are very minimal, thanks!

@mconcas mconcas merged commit 992316d into AliceO2Group:dev May 6, 2025
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@ChunzhengLab ChunzhengLab deleted the digi_its3 branch May 6, 2025 15:29
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@f3sch f3sch f3sch approved these changes

@mconcas mconcas mconcas approved these changes

@fgrosa fgrosa fgrosa approved these changes

@sawenzel sawenzel Awaiting requested review from sawenzel sawenzel is a code owner

@shahor02 shahor02 Awaiting requested review from shahor02 shahor02 is a code owner

@arossi81 arossi81 Awaiting requested review from arossi81 arossi81 is a code owner

@fprino fprino Awaiting requested review from fprino fprino is a code owner

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@ChunzhengLab @f3sch @alibuild @fgrosa @mconcas @shahor02