Missing CRC procedures for F7x#472
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* Document the fact (in comments) that the "Errata work-arounds" are completely mysterious. * update copyright year * Add comment for entire unit at top
Otherwise, as a range constraint, the result would be order-dependent on the parent type. Now use No_Output for the default value of the Output record component, to check for lack of a prior call to Initialize.
* Change ADT name to Audio_CODEC for closer match to documentation and meaningfulness * For the same reasons, change name Output_Device to Analog_Outputs. * Minor reordering to put the primary ADT declaration near the top of the package.
Affects: stm32-dma2d_bitmap, framebuffer_ltdc DMA2D_Fill_Rect was called without Synchronous => True, allowing DMA2D writes to the hidden framebuffer to still be in progress when Internal_Update_Layer flushed and handed the buffer to LTDC. Fix Fill_Rect to use Synchronous => True, consistent with Fill. Add Clean_DCache in Internal_Update_Layer covering the hidden buffer before Set_Frame_Buffer, ensuring CPU-written dirty cache lines are flushed to physical memory before LTDC DMA reads them. Add comments explaining the approach to the cache in Internal_Update_Layer
* add new declarations for Ethernet Physical Layer I/O Pins * add new procedures for enabling RMII clocks and pins
correct letter casing fix words changed in comments due to refactoring
* STM32.LTDC: - Add procedures Reload_Config_Async and Wait_For_Reload * Framebuffer_LTDC: - Add procedures Update_Layer_Async and Wait_For_Update. The new asynchronous versions request a register reload at the next vertical blank and return immediately; the Wait_* forms block until the LTDC has applied a pending reload (or return immediately when none is pending). The current synchronous Reload_Config / Update_Layer must wait for the LTDC to confirm the swap, which is paced by the display timing and can amount to up to one full vertical refresh interval of CPU dead time per call. Callers that fully repaint each frame and never read the now-hidden buffer get nothing useful for that wait. The additional asynchronous API lets them pipeline the swap with the next frame's draw preparation, for example, or other work that does not touch the now-hidden buffer, and resync explicitly only when an operation actually needs the new buffer state.
…d Cortex-M families. Created new directory arch/ARM/cortex_m/src/mpu_cm4_cm7/ and moved the two source files defining the MPU facility into that directory. Updated the scripts/config/archs.py file to include that new source directory for the supported MCU families (all the M4 and M7 boards, excluding the M0). Manually updated all the relevant gpr files to reference that new directory.
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Unlike the other devices with a CRC unit, the F7x STM32.Device package had the Enable_Clock routine but not the Disable_Clock and Reset procedures. Adding them here...