feat(pal): Enable MMU and caches on secondary PEs

[ashishsingha]

• Capture primary PE's MMU configuration during PE info table creation
• Secondary PEs now enable MMU and caches using primary PE's configuration
• Disable MMU and caches before PSCI CPU_OFF on secondary PEs
• This ensures consistent memory behavior across all PEs during test execution

[ashishsingha]

@chetan-rathore Please let me know what you think about it.

[chetan-rathore]

Hi @ashishsingha,

Thanks for your contribution— we’ll review the changes. Could you also share more details about the issue you observed that led to this update?

[ashishsingha]

Hi @ashishsingha,

Thanks for your contribution— we’ll review the changes. Could you also share more details about the issue you observed that led to this update?

Hi @chetan-rathore This is an enhancement where secondary CPUs won’t see timing delta while accessing any memory compared to primary CPU as now caches and MMUs will be enabled across the board. For example, if we change timer test to detect skew and drift in timer across CPUs, we need the execution environment to be same and optimal. It’ll help with performance related measurements too.

[SrikarJosyula]

Hi @ashishsingha,
Thanks for submitting the change. We're validating it on our side.

In the meanwhile, a minor comment on the implementation - ACS doesn’t need to disable the MMU and caches before powering off the secondary PEs, the cleanup should be handled by the EL3 firmware.
Also, when secondary PEs are powered on, SCTLR_ELx.{M, C, I} is expected to already be cleared, so consistent memory behavior should still be guaranteed. (Ref: Sections 5.5 & 6.4.3.4 of PSCI Spec)

The rest of the code looks good. We’ll share any findings from our validation.