Enhance PCIe Test Rule PCI_IN_19 to consider the DPC #192
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Include segment number as well while checking for the root port's bdf in the API val_pcie_parent_is_rootport(). Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Add support to disable & re-enable DPC during the execution of rule PCI_IN_19. This avoids unwanted DPC trigger and hence avoids link down event. Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
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@chetan-rathore Can you please check this? |
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Hi @ashishsingha, I am on holidays and will return on 4th Jan, adding @gowthamsiddarthd who will help in reviewing the changes. |
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Hi @tvidyasagar / @ashishsingha Thanks for catching this and for suggesting the change. Based on your suggestion, it looks like this behavior could be applicable to other tests as well, especially those that intentionally generate Unsupported Requests (URs). Disabling DPC centrally would help ensure that UR generation does not inadvertently bring the link down, allowing subsequent tests to continue accessing downstream devices. Given that, my suggestion would be to disable DPC during BDF table creation itself (around Let me know if you’re okay making this change, or if you’d prefer that I take care of it from my side. Regards, |
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@gowthamsiddarthd Thanks for taking the time to review. |
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Hi @gowthamsiddarthd |
- Introduce `val_pcie_enable_dpc()` and `val_pcie_disable_dpc()` helper functions to manage DPC trigger enable bits in the DPC capability structure. - Use these APIs to disable DPC for all Root Ports and Downstream Ports during PCIe device table creation to avoid unintended error signaling. - Update Exerciser test e024 to call the new API for disabling DPC instead of manually clearing control register bits. - Update relevant headers and extend copyright year to 2026. - Fixes ARM-software#192 Change-Id: I8450efdc15d582bdbbddc90a8c885991613039e5
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This patch series enhances the PCIe Test Rule PCI_IN_19 to disable the DPC (if enabled already). Disabling the DPC makes sure that the link will not go down because of the Unsupported Request generation and ensures that the tests that get executed after PCI_IN_19 continue to have access to the downstream devices. If the DPC is enabled, UR generation can potentially trigger DPC and the link goes down and any further accesses to the downstream hierarchy will not take place.