CMSIS: add ARMv8-A AARCH64 support

CMSIS/Core_AArch64/Include/CMSIS_Include_core_aarch64.cmake

@@ -0,0 +1,12 @@
+#Description: CMSIS Include For Cortex-A; user_visible: True
+include_guard(GLOBAL)
+message("CMSIS_Include_core_ca component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/../Source/cache_armv8a.c
+    ${CMAKE_CURRENT_LIST_DIR}/../Source/mmu_armv8a.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)

CMSIS/Core_AArch64/Include/cache_armv8a.h

@@ -0,0 +1,131 @@
+/**************************************************************************//**
+ * @file     cache_armv8a.h
+ * @brief    CMSIS AARCH64 Cache API header file
+ * @version  V1.0.0
+ * @date     21. January 2022
+ ******************************************************************************/
+
+/*
+ * Copyright 2022-2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CACHE_ARMV8A_H
+#define __CACHE_ARMV8A_H
+
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define dcache_ops(op, operand)				\
+({							\
+	__asm__ volatile ("dc " __STRINGIFY(op) ", %0"	\
+			  ::"r" (operand): "memory");	\
+})
+
+
+/* Invalidate instruction cache by virtual address to PoU */
+static inline void icache_invalidate_range(uintptr_t addr, size_t size)
+{
+	uintptr_t cur = addr;
+	uintptr_t end_addr = cur + size;
+
+	/* Align address to line size */
+	cur &= ~(ICACHE_LINE_SIZE - 1);
+
+	do {
+		__asm__ volatile ("ic ivau, %0" ::"r" (cur): "memory");
+		cur += ICACHE_LINE_SIZE;
+	} while (cur < end_addr);
+
+	__DSB();
+	__ISB();
+}
+
+/* Invalidate all instruction cache to PoU */
+static inline void icache_invalidate_all(void)
+{
+	__asm__ volatile ("ic iallu" ::: "memory");
+	__DSB();
+	__ISB();
+}
+
+/* Clean data cache by virtual address to PoC */
+static inline void dcache_clean_range(uintptr_t addr, size_t size)
+{
+	uintptr_t cur = addr;
+	uintptr_t end = addr + size;
+
+	/* Align address to line size */
+	cur &= ~(DCACHE_LINE_SIZE - 1);
+
+	while (cur < end) {
+		dcache_ops(cvac, cur);
+		cur += DCACHE_LINE_SIZE;
+	}
+
+	__DSB();
+}
+
+/* Invalidate data cache by virtual address to PoC */
+static inline void dcache_invalidate_range(uintptr_t addr, size_t size)
+{
+	uintptr_t cur = addr;
+	uintptr_t end = addr + size;
+
+	if (end & (DCACHE_LINE_SIZE - 1)) {
+		end &= ~(DCACHE_LINE_SIZE - 1);
+		dcache_ops(civac, end);
+	}
+
+	if (cur & (DCACHE_LINE_SIZE - 1)) {
+		cur &= ~(DCACHE_LINE_SIZE - 1);
+		if (cur != end)
+			dcache_ops(civac, cur);
+		cur += DCACHE_LINE_SIZE;
+	}
+
+	while (cur < end) {
+		dcache_ops(ivac, cur);
+		cur += DCACHE_LINE_SIZE;
+	}
+
+	__DSB();
+}
+
+/* Clean and invalidate data cache by virtual address to PoC */
+static inline void dcache_clean_invalidate_range(uintptr_t addr, size_t size)
+{
+	uintptr_t cur = addr;
+	uintptr_t end = addr + size;
+
+	/* Align address to line size */
+	cur &= ~(DCACHE_LINE_SIZE - 1);
+
+	while (cur < end) {
+		dcache_ops(civac, cur);
+		cur += DCACHE_LINE_SIZE;
+	}
+
+	__DSB();
+}
+
+void dcache_clean_all(void);
+void dcache_invalidate_all(void);
+void dcache_clean_invalidate_all(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CACHE_ARMV8A_H */

CMSIS/Core_AArch64/Include/cmsis_compiler.h

@@ -0,0 +1,92 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V1.0.0
+ * @date     05. october 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright 2021-2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Define compiler macros for CPU architecture, if not yet defined by the
+ * compiler default macros
+ */
+#if __ARM_ARCH_8A__
+/* Macro already defined */
+#else
+  #if defined(__ARM_ARCH_8A) && __ARM_ARCH_8A == 1
+    #define __ARM_ARCH_8A__ 1
+  #endif /* __ARM_ARCH_8A == 1 */
+#endif
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iar.h"
+
+#else
+  #error Unknown compiler
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_COMPILER_H */