parameterized_loadable_counter.v

/**
 * Parameterized Loadable Counter
 * 
 * This module implements a loadable counter that can count up or load a
 * parallel value. It provides both counting and loading capabilities,
 * making it useful for applications requiring programmable count values.
 * 
 * Key Features:
 * - Up counter: Increments on each enable
 * - Parallel load: Loads data_in when load is asserted
 * - Enable control: Can pause/resume counting
 * - Priority: Load has higher priority than count
 * - Configurable width: Any bit width via WIDTH parameter
 * 
 * Operation Modes:
 * - Load mode (load=1): Loads data_in into counter (highest priority)
 * - Count mode (load=0, enable=1): Increments counter
 * - Hold mode (load=0, enable=0): Maintains current value
 * 
 * Priority:
 * - Load operation has highest priority
 * - Count operation occurs only if load is not asserted
 * 
 * Use Cases:
 * - Programmable timers
 * - Event counters with preset values
 * - Down counters (by loading complement)
 * - Frequency dividers
 * - Timeout counters
 * 
 * @param WIDTH Width of counter (default: 8 bits)
 * 
 * @input clk Clock signal
 * @input rst_n Active-low reset signal
 * @input enable Enable counting (high to count)
 * @input load Load enable (high to load data_in)
 * @input data_in[WIDTH-1:0] Parallel data to load
 * @output count[WIDTH-1:0] Counter output value
 */
module parameterized_loadable_counter #(
    parameter WIDTH = 8
)(
    input wire clk,
    input wire rst_n,                // Active low reset
    input wire enable,               // Enable signal
    input wire load,                 // Load control signal
    input wire [WIDTH-1:0] data_in,  // Parallel data input
    output wire [WIDTH-1:0] count
);

    reg [WIDTH-1:0] counter_reg;
    
    // Reset counter to 0
    initial begin
        counter_reg = {WIDTH{1'b0}};
    end
    
    // ============================================================================
    // Counter Logic
    // ============================================================================
    // Updates counter based on reset, load, or count operations
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            // ====================================================================
            // Reset State
            // ====================================================================
            // Reset counter to zero
            counter_reg <= {WIDTH{1'b0}};
        end else if (load) begin
            // ====================================================================
            // Parallel Load (Highest Priority)
            // ====================================================================
            // Load parallel data into counter
            // This has priority over count operation
            counter_reg <= data_in;
        end else if (enable) begin
            // ====================================================================
            // Count Operation
            // ====================================================================
            // Increment counter when enable is high and load is not asserted
            counter_reg <= counter_reg + 1'b1;
        end
        // Note: If neither load nor enable is asserted, counter holds its value
    end
    
    // Connect the internal register to the output
    assign count = counter_reg;

endmodule