Skip to content

Commit b1ccaba

Browse files
lyakhlgirdwood
lyakh
authored and
lgirdwood
committed
build: restore interrupt.h files to fix AMD Zephyr build
Turns out that two XTOS-specific interrupt.h files deleted by b8266ae ("build: delete more XTOS-only files") and d07ac09 ("build: remove obvioux XTOS-only files") breaks AMD Zephyr builds, restore them to the state before those commits. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
1 parent b315920 commit b1ccaba

File tree

2 files changed

+314
-0
lines changed

2 files changed

+314
-0
lines changed

‎src/arch/xtensa/include/arch/drivers/interrupt.h‎

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,97 @@
1+
/* SPDX-License-Identifier: BSD-3-Clause
2+
*
3+
* Copyright(c) 2016 Intel Corporation. All rights reserved.
4+
*
5+
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
6+
*/
7+
8+
#ifdef __SOF_DRIVERS_INTERRUPT_H__
9+
10+
#ifndef __ARCH_DRIVERS_INTERRUPT_H__
11+
#define __ARCH_DRIVERS_INTERRUPT_H__
12+
13+
#include <xtensa/hal.h>
14+
#include <xtensa/xtruntime.h>
15+
#include <stddef.h>
16+
#include <stdint.h>
17+
18+
19+
static inline int arch_interrupt_register(int irq,
20+
void (*handler)(void *arg), void *arg)
21+
{
22+
xthal_set_intclear(0x1 << irq);
23+
_xtos_set_interrupt_handler_arg(irq, handler, arg);
24+
return 0;
25+
}
26+
27+
static inline void arch_interrupt_unregister(int irq)
28+
{
29+
_xtos_set_interrupt_handler_arg(irq, NULL, NULL);
30+
}
31+
32+
/* returns previous mask */
33+
#define arch_interrupt_enable_mask(mask) \
34+
_xtos_ints_on(mask)
35+
36+
/* returns previous mask */
37+
#define arch_interrupt_disable_mask(mask) \
38+
_xtos_ints_off(mask)
39+
40+
static inline uint32_t arch_interrupt_get_level(void)
41+
{
42+
uint32_t level;
43+
44+
__asm__ __volatile__(
45+
" rsr.ps %0\n"
46+
" extui %0, %0, 0, 4\n"
47+
: "=&a" (level) :: "memory");
48+
49+
return level;
50+
}
51+
52+
static inline void arch_interrupt_set(int irq)
53+
{
54+
xthal_set_intset(0x1 << irq);
55+
}
56+
57+
static inline void arch_interrupt_clear(int irq)
58+
{
59+
xthal_set_intclear(0x1 << irq);
60+
}
61+
62+
static inline uint32_t arch_interrupt_get_enabled(void)
63+
{
64+
return xthal_get_intenable();
65+
}
66+
67+
static inline uint32_t arch_interrupt_get_status(void)
68+
{
69+
return xthal_get_interrupt();
70+
}
71+
72+
static inline uint32_t arch_interrupt_global_disable(void)
73+
{
74+
uint32_t flags;
75+
76+
__asm__ __volatile__("rsil %0, 5"
77+
: "=a" (flags) :: "memory");
78+
return flags;
79+
}
80+
81+
static inline void arch_interrupt_global_enable(uint32_t flags)
82+
{
83+
__asm__ __volatile__("wsr %0, ps; rsync"
84+
:: "a" (flags) : "memory");
85+
}
86+
87+
#if CONFIG_WAKEUP_HOOK
88+
void arch_interrupt_on_wakeup(void);
89+
#endif
90+
91+
#endif /* __ARCH_DRIVERS_INTERRUPT_H__ */
92+
93+
#else
94+
95+
#error "This file shouldn't be included from outside of sof/drivers/interrupt.h"
96+
97+
#endif /* __SOF_INTERRUPT_H__ */

‎xtos/include/rtos/interrupt.h‎

Lines changed: 217 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,217 @@
1+
/* SPDX-License-Identifier: BSD-3-Clause
2+
*
3+
* Copyright(c) 2018 Intel Corporation. All rights reserved.
4+
*
5+
* Author: Janusz Jankowski <janusz.jankowski@linux.intel.com>
6+
*/
7+
8+
#ifndef __SOF_DRIVERS_INTERRUPT_H__
9+
#define __SOF_DRIVERS_INTERRUPT_H__
10+
11+
#include <platform/drivers/interrupt.h>
12+
13+
#if !defined(__ASSEMBLER__) && !defined(LINKER)
14+
#include <arch/drivers/interrupt.h>
15+
#include <sof/lib/cpu.h>
16+
#include <sof/list.h>
17+
#include <rtos/sof.h>
18+
#include <rtos/spinlock.h>
19+
#include <sof/trace/trace.h>
20+
#include <user/trace.h>
21+
#include <stdbool.h>
22+
#include <stdint.h>
23+
24+
/**
25+
* \brief child IRQ descriptor for cascading IRQ controllers.
26+
*/
27+
struct irq_child {
28+
int enable_count[CONFIG_CORE_COUNT]; /**< IRQ enable counter */
29+
struct list_item list; /**< head for IRQ descriptors,
30+
* sharing this interrupt
31+
*/
32+
};
33+
34+
/**
35+
* \brief interrupt client descriptor
36+
*/
37+
struct irq_desc {
38+
int irq; /**< virtual IRQ number */
39+
void (*handler)(void *arg); /**< interrupt handler function */
40+
void *handler_arg; /**< interrupt handler argument */
41+
uint32_t cpu_mask; /**< a mask of CPUs on which this
42+
* interrupt is enabled
43+
*/
44+
struct list_item irq_list; /**< to link to other irq_desc */
45+
};
46+
47+
/**
48+
* \brief cascading IRQ controller operations.
49+
*/
50+
struct irq_cascade_ops {
51+
void (*mask)(struct irq_desc *desc, uint32_t irq,
52+
unsigned int cpu); /**< mask */
53+
void (*unmask)(struct irq_desc *desc, uint32_t irq,
54+
unsigned int cpu); /**< unmask */
55+
};
56+
57+
/**
58+
* \brief cascading interrupt controller descriptor.
59+
*/
60+
struct irq_cascade_desc {
61+
const char *name; /**< name of the
62+
* controller
63+
*/
64+
int irq_base; /**< first virtual IRQ
65+
* number, assigned to
66+
* this controller
67+
*/
68+
const struct irq_cascade_ops *ops; /**< cascading interrupt
69+
* controller driver
70+
* operations
71+
*/
72+
struct irq_desc desc; /**< the interrupt, that
73+
* this controller is
74+
* generating
75+
*/
76+
struct irq_cascade_desc *next; /**< link to the global
77+
* list of interrupt
78+
* controllers
79+
*/
80+
bool global_mask; /**< the controller
81+
* cannot mask input
82+
* interrupts per core
83+
*/
84+
struct k_spinlock lock; /**< protect child
85+
* lists, enable and
86+
* child counters
87+
*/
88+
int enable_count[CONFIG_CORE_COUNT]; /**< enabled child
89+
* interrupt counter
90+
*/
91+
unsigned int num_children[CONFIG_CORE_COUNT]; /**< number of children
92+
*/
93+
struct irq_child child[PLATFORM_IRQ_CHILDREN]; /**< array of child
94+
* lists - one per
95+
* multiplexed IRQ
96+
*/
97+
};
98+
99+
/* A descriptor for cascading interrupt controller template */
100+
struct irq_cascade_tmpl {
101+
const char *name;
102+
const struct irq_cascade_ops *ops;
103+
int irq;
104+
void (*handler)(void *arg);
105+
bool global_mask;
106+
};
107+
108+
/**
109+
* \brief Cascading interrupt controller root.
110+
*/
111+
struct cascade_root {
112+
struct k_spinlock lock; /**< locking mechanism */
113+
struct irq_cascade_desc *list; /**< list of child cascade irqs */
114+
int last_irq; /**< last registered cascade irq */
115+
};
116+
117+
static inline struct cascade_root *cascade_root_get(void)
118+
{
119+
return sof_get()->cascade_root;
120+
}
121+
122+
/* For i.MX, while building SOF with Zephyr use the interrupt_*
123+
* functions from second level interrupt handling and IRQ_STEER.
124+
*/
125+
#if defined(__ZEPHYR__) && (defined(CONFIG_IMX) || defined(CONFIG_AMD))
126+
int mux_interrupt_get_irq(unsigned int irq, const char *cascade);
127+
int mux_interrupt_register(uint32_t irq, void(*handler)(void *arg), void *arg);
128+
void mux_interrupt_unregister(uint32_t irq, const void *arg);
129+
uint32_t mux_interrupt_enable(uint32_t irq, void *arg);
130+
uint32_t mux_interrupt_disable(uint32_t irq, void *arg);
131+
#endif
132+
133+
int interrupt_register(uint32_t irq, void(*handler)(void *arg), void *arg);
134+
void interrupt_unregister(uint32_t irq, const void *arg);
135+
uint32_t interrupt_enable(uint32_t irq, void *arg);
136+
uint32_t interrupt_disable(uint32_t irq, void *arg);
137+
138+
/* Zephyr compat */
139+
#if !defined(__ZEPHYR__)
140+
#define arch_irq_lock() arch_interrupt_disable_mask(0xffffffff)
141+
#endif
142+
143+
void platform_interrupt_init(void);
144+
145+
void platform_interrupt_set(uint32_t irq);
146+
void platform_interrupt_clear(uint32_t irq, uint32_t mask);
147+
uint32_t platform_interrupt_get_enabled(void);
148+
void interrupt_mask(uint32_t irq, unsigned int cpu);
149+
void interrupt_unmask(uint32_t irq, unsigned int cpu);
150+
151+
/*
152+
* On platforms, supporting cascading interrupts cascaded interrupt numbers
153+
* are greater than or equal to PLATFORM_IRQ_HW_NUM
154+
*/
155+
#define interrupt_is_dsp_direct(irq) (!PLATFORM_IRQ_CHILDREN || \
156+
irq < PLATFORM_IRQ_HW_NUM)
157+
158+
void interrupt_init(struct sof *sof);
159+
int interrupt_cascade_register(const struct irq_cascade_tmpl *tmpl);
160+
struct irq_cascade_desc *interrupt_get_parent(uint32_t irq);
161+
int interrupt_get_irq(unsigned int irq, const char *cascade);
162+
163+
static inline void interrupt_set(int irq)
164+
{
165+
platform_interrupt_set(irq);
166+
}
167+
168+
static inline void interrupt_clear_mask(int irq, uint32_t mask)
169+
{
170+
platform_interrupt_clear(irq, mask);
171+
}
172+
173+
static inline void interrupt_clear(int irq)
174+
{
175+
interrupt_clear_mask(irq, 1);
176+
}
177+
178+
static inline uint32_t interrupt_global_disable(void)
179+
{
180+
return arch_interrupt_global_disable();
181+
}
182+
183+
static inline void interrupt_global_enable(uint32_t flags)
184+
{
185+
arch_interrupt_global_enable(flags);
186+
}
187+
188+
#if CONFIG_LIBRARY
189+
190+
/* temporary fix to remove build warning for testbench that will need shortly
191+
* realigned when Zephyr native APIs are used.
192+
*/
193+
static inline void __irq_local_disable(unsigned long flags) {}
194+
static inline void __irq_local_enable(unsigned long flags) {}
195+
196+
/* disables all IRQ sources on current core - NO effect on library */
197+
#define irq_local_disable(flags) \
198+
do { \
199+
flags = 0; \
200+
__irq_local_disable(flags); \
201+
} while (0)
202+
203+
/* re-enables IRQ sources on current core - NO effect on library*/
204+
#define irq_local_enable(flags) \
205+
__irq_local_enable(flags)
206+
207+
#else
208+
/* disables all IRQ sources on current core */
209+
#define irq_local_disable(flags) \
210+
(flags = interrupt_global_disable())
211+
212+
/* re-enables IRQ sources on current core */
213+
#define irq_local_enable(flags) \
214+
interrupt_global_enable(flags)
215+
#endif
216+
#endif
217+
#endif /* __SOF_DRIVERS_INTERRUPT_H__ */

0 commit comments

Comments
 (0)