platform: mtk: wire native Zephyr DMA/DAI into build and platform init

Register sof_dma[] entries, allocate dma_chan_data[] arrays in
platform_init(), add CONFIG_DMA_MTK_SOF_HOST_DMA Kconfig symbol,
guard legacy-only code paths, and enable native drivers for MT8196.

Signed-off-by: Cyril Chao <cyril.chao@mediatek.corp-partner.google.com>

Author: Cyril Chao

app/boards/mt8196_mt8196_adsp.conf

@@ -5,3 +5,6 @@
 # config goes in prj.conf.
 CONFIG_MTK=y
 CONFIG_RIMAGE_SIGNING_SCHEMA="mt8196"
+CONFIG_ZEPHYR_NATIVE_DRIVERS=y
+CONFIG_DMA=y
+CONFIG_DAI=y

src/ipc/ipc3/host-page-table.c

@@ -98,7 +98,8 @@ static int ipc_get_page_descriptors(struct sof_dma *dmac, uint8_t *page_table,
 	 * reload() function which may not be the case for all
 	 * vendors.
 	 */
-	if (!IS_ENABLED(CONFIG_DMA_NXP_SOF_HOST_DMA)) {
+	if (!IS_ENABLED(CONFIG_DMA_NXP_SOF_HOST_DMA) &&
+	    !IS_ENABLED(CONFIG_DMA_MTK_SOF_HOST_DMA)) {
 		tr_err(&ipc_tr, "DMAC not supported for page transfer");
 		return -ENOTSUP;
 	}

src/platform/Kconfig

@@ -312,7 +312,7 @@ config MT8365
 
 config MTK
 	bool "Build for Mediatek (Zephyr)"
-	select SCHEDULE_DMA_MULTI_CHANNEL
+	select SCHEDULE_DMA_MULTI_CHANNEL if !ZEPHYR_NATIVE_DRIVERS
 	select HOST_PTABLE
 	help
 	  Select if your target is a Mediatek DSP.  Builds Zephyr firmware.

src/platform/mtk/dai.c

@@ -1,9 +1,14 @@
 // SPDX-License-Identifier: BSD-3-Clause
 // Copyright(c) 2024 Google LLC.  All rights reserved.
 // Author: Andy Ross <andyross@google.com>
+#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS
 #include <sof/lib/dai-legacy.h>
+#endif
 #include <ipc/dai.h>
 #include <sof/drivers/afe-drv.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <zephyr/devicetree.h>
 
 /* The legacy driver stores register addresses as an offset from an
  * arbitrary base address (which is not actually a unified block of
@@ -158,6 +163,7 @@ static struct mtk_base_memif_data afe_memifs[] = {
 	DT_FOREACH_STATUS_OKAY(mediatek_afe, EMPTY_STRUCT)
 };
 
+#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS
 static struct dai mtk_dais[] = {
 	DT_FOREACH_STATUS_OKAY(mediatek_afe, EMPTY_STRUCT)
 };
@@ -210,6 +216,7 @@ static const struct dai_info mtk_dai_info = {
 	.dai_type_array = mtk_dai_types,
 	.num_dai_types = ARRAY_SIZE(mtk_dai_types),
 };
+#endif /* !CONFIG_ZEPHYR_NATIVE_DRIVERS */
 
 #if defined(CONFIG_SOC_SERIES_MT818X) || defined(CONFIG_SOC_MT8195)
 static unsigned int mtk_afe2adsp_addr(unsigned int addr)
@@ -324,7 +331,7 @@ struct mtk_base_afe_platform mtk_afe_platform = {
 	.memif_32bit_supported = 0,
 	.irq_datas = NULL,
 	.irqs_size = 0,
-	.dais_size = ARRAY_SIZE(mtk_dais),
+	.dais_size = ARRAY_SIZE(afes),
 	.afe_fs = mtk_afe_fs,
 	.irq_fs = mtk_afe_fs_timing,
 #if defined(CONFIG_SOC_SERIES_MT818X) || defined(CONFIG_SOC_MT8195)
@@ -342,6 +349,7 @@ int mtk_dai_init(struct sof *sof)
 		afe_memifs[i].id = i;
 		cfg_convert(&afes[i], &afe_memifs[i]);
 
+#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS
 		/* Also initialize the dais array */
 		extern const struct dai_driver afe_dai_driver;
 
@@ -362,6 +370,7 @@ int mtk_dai_init(struct sof *sof)
 		int hs = (i << 16) | di;
 
 		mtk_dais[di].plat_data.fifo[0].handshake = hs;
+#endif
 	}
 
 	/* DTS stores the direction as a boolean property, but the
@@ -377,7 +386,9 @@ int mtk_dai_init(struct sof *sof)
 	for (/**/; i < ARRAY_SIZE(afes); i++)
 		__ASSERT_NO_MSG(!afes[i].downlink);
 
+#ifndef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	sof->dai_info = &mtk_dai_info;
 	sof->dma_info = &mtk_dma_info;
+#endif
 	return 0;
 }

src/platform/mtk/platform.c

@@ -157,8 +157,13 @@ struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
 int platform_ipc_init(struct ipc *ipc)
 {
 	mtk_host_buffer.page_table = hostbuf_ptable;
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
+	mtk_host_buffer.dmac = sof_dma_get(SOF_DMA_DIR_HMEM_TO_LMEM, 0,
+					    SOF_DMA_DEV_HOST, SOF_DMA_ACCESS_SHARED);
+#else
 	mtk_host_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST,
 				       DMA_ACCESS_SHARED);
+#endif
 
 	schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(zipc_task_uuid),
 			       &ipc_task_ops, ipc, 0, 0);
@@ -210,18 +215,63 @@ void clocks_init(struct sof *sof)
 	sof->clocks = clks;
 }
 
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
+/*
+ * Allocate SOF-level channel descriptor arrays (struct dma_chan_data[]) for
+ * each sof_dma entry. Native Zephyr DMA drivers manage their own internal
+ * channel state but do not allocate the SOF-layer chan[] array that
+ * dai-zephyr.c and host-zephyr.c rely on (e.g. dd->chan = &dd->dma->chan[i]).
+ * Legacy DMA drivers (dummy-dma, afe-memif) did this in their own probe();
+ * in the native path we do it here after dmac_init() registers the DMA info.
+ */
+static int mtk_dma_chan_alloc(struct sof *sof)
+{
+	int i, j;
+
+	for (i = 0; i < sof->dma_info->num_dmas; i++) {
+		struct sof_dma *d = &sof->dma_info->dma_array[i];
+
+		if (!d->plat_data.channels || d->chan)
+			continue;
+
+		d->chan = rzalloc(SOF_MEM_FLAG_KERNEL,
+				  d->plat_data.channels * sizeof(struct dma_chan_data));
+		if (!d->chan)
+			return -ENOMEM;
+
+		for (j = 0; j < d->plat_data.channels; j++) {
+			d->chan[j].dma = d;
+			d->chan[j].index = j;
+		}
+	}
+
+	return 0;
+}
+#endif
+
 int platform_init(struct sof *sof)
 {
+	int ret;
+
 	clocks_init(sof);
 	scheduler_init_edf();
 	sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK);
 	scheduler_init_ll(sof->platform_timer_domain);
 	mtk_dai_init(sof);
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
+	/* In native mode, DMA is registered in sof/zephyr/lib/dma.c */
+	dmac_init(sof);
+	ret = mtk_dma_chan_alloc(sof);
+	if (ret < 0)
+		return ret;
+#endif
 	ipc_init(sof);
+#if CONFIG_SCHEDULE_DMA_MULTI_CHANNEL
 	sof->platform_dma_domain =
 		dma_multi_chan_domain_init(&sof->dma_info->dma_array[0],
 					   sof->dma_info->num_dmas,
 					   PLATFORM_DEFAULT_CLOCK, false);
+#endif
 	sa_init(sof, CONFIG_SYSTICK_PERIOD);
 	return 0;
 }

zephyr/CMakeLists.txt

@@ -518,11 +518,25 @@ if (CONFIG_SOC_FAMILY_MTK)
 	zephyr_library_sources(
 		${SOF_PLATFORM_PATH}/mtk/platform.c
 		${SOF_PLATFORM_PATH}/mtk/dai.c
-		${SOF_DRIVERS_PATH}/generic/dummy-dma.c
-		${SOF_SRC_PATH}/drivers/mediatek/afe/afe-memif.c
-		${SOF_SRC_PATH}/drivers/mediatek/afe/afe-dai.c
 		${SOF_SRC_PATH}/drivers/mediatek/afe/afe-drv.c
 	)
+
+	if (CONFIG_ZEPHYR_NATIVE_DRIVERS)
+		# Native Zephyr DMA/DAI path
+		zephyr_library_sources(
+			lib/dma.c
+			${SOF_SRC_PATH}/drivers/mediatek/afe/zephyr_mtk_afe_memif.c
+			${SOF_SRC_PATH}/drivers/mediatek/afe/zephyr_mtk_host_dma.c
+			${SOF_SRC_PATH}/drivers/mediatek/afe/zephyr_mtk_dai.c
+		)
+	else()
+		# Legacy DMA path
+		zephyr_library_sources(
+			${SOF_DRIVERS_PATH}/generic/dummy-dma.c
+			${SOF_SRC_PATH}/drivers/mediatek/afe/afe-memif.c
+			${SOF_SRC_PATH}/drivers/mediatek/afe/afe-dai.c
+		)
+	endif()
 endif()
 
 # Building for native_posix-based whole-OS host emulator

zephyr/Kconfig

@@ -169,6 +169,14 @@ config ZEPHYR_NATIVE_DRIVERS
 	  dai-zephyr
 	  will be used instead of legacy xtos version.
 
+config DMA_MTK_SOF_HOST_DMA
+	bool "MediaTek SOF host DMA driver"
+	default y if SOC_FAMILY_MTK && ZEPHYR_NATIVE_DRIVERS
+	help
+	  Software-based DMA driver for MTK SOF host component.
+	  MTK DSP can access host memory directly, so this driver
+	  implements DMA transfers using memcpy + cache management.
+
 config DMA_DOMAIN
 	bool "Enable the usage of DMA domain."
 	help

zephyr/lib/dma.c

@@ -239,6 +239,28 @@ SHARED_DATA struct sof_dma dma[] = {
 	.z_dev = DEVICE_DT_GET(DT_NODELABEL(acp_sdw_dma)),
 },
 #endif
+#if DT_HAS_COMPAT_STATUS_OKAY(mediatek_afe_memif_dma)
+{
+	.plat_data = {
+		.dir		= SOF_DMA_DIR_MEM_TO_DEV | SOF_DMA_DIR_DEV_TO_MEM,
+		.devs		= SOF_DMA_DEV_AFE_MEMIF,
+		.channels	= DT_PROP(DT_NODELABEL(afe_memif_dma), dma_channels),
+		.period_count	= 4,
+	},
+	.z_dev		= DEVICE_DT_GET(DT_NODELABEL(afe_memif_dma)),
+},
+#endif
+#if DT_HAS_COMPAT_STATUS_OKAY(mediatek_sof_host_dma)
+{
+	.plat_data = {
+		.dir		= SOF_DMA_DIR_HMEM_TO_LMEM | SOF_DMA_DIR_LMEM_TO_HMEM,
+		.devs		= SOF_DMA_DEV_HOST,
+		.channels	= DT_PROP(DT_NODELABEL(host_dma), dma_channels),
+		.period_count	= 4,
+	},
+	.z_dev		= DEVICE_DT_GET(DT_NODELABEL(host_dma)),
+},
+#endif
 };
 
 const struct dma_info lib_dma = {