ipc: ipc4: make native Zephyr drivers mandatory for IPC4

Remove old code to support IPC4 use with non-Zephyr DAI and DMA drivers.
This code was used to transition to Zephyr, but now all active users of
IPC4 have moved to native Zephyr drivers, so there are no users for this
code left.

Add a Kconfig dependency to native driver support.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>

Author: kv2019i

src/ipc/Kconfig

@@ -14,6 +14,7 @@ config IPC_MAJOR_3
 
 config IPC_MAJOR_4
 	bool "IPC Major Version 4"
+	depends on ZEPHYR_NATIVE_DRIVERS
 	help
 	  This is an IPC version used by certain middleware on some IOT
 	  Intel devices. Not for general use.

src/ipc/ipc4/dai.c

@@ -143,9 +143,7 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev)
 {
 	struct ipc_config_dai *dai = &dd->ipc_config;
 	struct ipc4_copier_module_cfg *copier_cfg = dd->dai_spec_config;
-#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	struct dai *dai_p = dd->dai;
-#endif
 
 	if (!dai) {
 		comp_err(dev, "no dai!\n");
@@ -174,12 +172,7 @@ int ipc_dai_data_config(struct dai_data *dd, struct comp_dev *dev)
 	case SOF_DAI_INTEL_HDA:
 		break;
 	case SOF_DAI_INTEL_ALH:
-#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 		dd->stream_id = dai_get_stream_id(dai_p, dai->direction);
-#else
-		/* only native Zephyr driver supported */
-		return -EINVAL;
-#endif
 		/* SDW HW FIFO always requires 32bit MSB aligned sample data for
 		 * all formats, such as 8/16/24/32 bits.
 		 */
@@ -243,15 +236,10 @@ void dai_dma_release(struct dai_data *dd, struct comp_dev *dev)
 		 * pause to stop.
 		 * TODO: refine power management when stream is paused
 		 */
-#if CONFIG_ZEPHYR_NATIVE_DRIVERS
 		/* if reset is after pause dma has already been stopped */
 		dma_stop(dd->chan->dma->z_dev, dd->chan->index);
 
 		dma_release_channel(dd->chan->dma->z_dev, dd->chan->index);
-#else
-		dma_stop_legacy(dd->chan);
-		dma_channel_put_legacy(dd->chan);
-#endif
 		dd->chan->dev_data = NULL;
 		dd->chan = NULL;
 	}
@@ -425,7 +413,6 @@ __cold int dai_config(struct dai_data *dd, struct comp_dev *dev,
 			      copier_cfg->gtw_cfg.config_data, size);
 }
 
-#if CONFIG_ZEPHYR_NATIVE_DRIVERS
 int dai_common_position(struct dai_data *dd, struct comp_dev *dev,
 			struct sof_ipc_stream_posn *posn)
 {
@@ -477,51 +464,3 @@ void dai_dma_position_update(struct dai_data *dd, struct comp_dev *dev)
 
 	mailbox_sw_regs_write(dd->slot_info.reg_offset, &slot, sizeof(slot));
 }
-#else
-int dai_common_position(struct dai_data *dd, struct comp_dev *dev,
-			struct sof_ipc_stream_posn *posn)
-{
-	struct dma_chan_status status;
-
-	/* total processed bytes count */
-	posn->dai_posn = dd->total_data_processed;
-
-	platform_dai_wallclock(dev, &dd->wallclock);
-	posn->wallclock = dd->wallclock;
-
-	status.ipc_posn_data = &posn->comp_posn;
-	dma_status_legacy(dd->chan, &status, dev->direction);
-
-	return 0;
-}
-
-int dai_position(struct comp_dev *dev, struct sof_ipc_stream_posn *posn)
-{
-	struct dai_data *dd = comp_get_drvdata(dev);
-
-	return dai_common_position(dd, dev, posn);
-}
-
-void dai_dma_position_update(struct dai_data *dd, struct comp_dev *dev)
-{
-	struct ipc4_llp_reading_slot slot;
-	struct dma_chan_status status;
-	uint32_t llp_data[2];
-
-	if (!dd->slot_info.node_id)
-		return;
-
-	status.ipc_posn_data = llp_data;
-	dma_status_legacy(dd->chan, &status, dev->direction);
-
-	platform_dai_wallclock(dev, &dd->wallclock);
-
-	slot.node_id = dd->slot_info.node_id;
-	slot.reading.llp_l = llp_data[0];
-	slot.reading.llp_u = llp_data[1];
-	slot.reading.wclk_l = (uint32_t)dd->wallclock;
-	slot.reading.wclk_u = (uint32_t)(dd->wallclock >> 32);
-
-	mailbox_sw_regs_write(dd->slot_info.reg_offset, &slot, sizeof(slot));
-}
-#endif