These two simulation files needed? #1334
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Hi, When we test this on board, xc7a100tcsg324-1 My understanding is ROM is pre-loaded and uart terminals of Neorv32 are connected to UART(via USB2UART bridge). |
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Replies: 3 comments
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I just synthesized and programmed the board without these files and it still worked. |
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This is correct for an actual (physical) implementation.
All the sources in However, for Vivado it does not hurt if they are added to the |
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Thank you. |
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This is correct for an actual (physical) implementation.
All the sources in
simare only required for simulation and are (in most cases) not synthesizable anyway.However, for Vivado it does not hurt if they are added to the
fileset_simfile set, as these files are only used for simulation and not for the actual implementation.