Just to know about PULP Design Verification side

[arunvthampi]

Hi,
I am Design Verification Engineer. I would like to do the design verification for the PULP SoC. I could see that tb side was made with normal sv and not a UVM based approach. Are there any meetings or discussions taking place as I would like to join and contribute to as much as I could after my office hours.

Sorry for placing my thoughts in issue.
Would like to hear a reply.

Thanks & regards,