Port to ZedBoard

[k0nze]

Hello there,
I'm trying to synthesize bigpulp for the ZedBoard. After setting the appropriate paths to Synopsys DesignWare, setting BOARD to zedboard in fpga/sourceme.sh and executing the following commands:

./update-ips
cd fpga
source sourceme.sh
make ips
make synth-pulp_cluster

I get the following error messages when Vivado 2017.02 elaborates icache_bank_mp_128:

INFO: [Synth 8-638] synthesizing module 'icache_bank_mp_128' [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/icache_mp_128_pf/RTL/icache_bank_mp_128.sv:48]
        Parameter FETCH_ADDR_WIDTH bound to: 32 - type: integer
        Parameter FETCH_DATA_WIDTH bound to: 128 - type: integer
        Parameter NB_CORES bound to: 3 - type: integer
        Parameter BANK_ID bound to: 0 - type: integer
        Parameter NB_BANKS bound to: 1 - type: integer
        Parameter NB_WAYS bound to: 4 - type: integer
        Parameter CACHE_LINE bound to: 1 - type: integer
        Parameter SCM_ADDR_WIDTH bound to: 4 - type: integer
        Parameter SCM_TAG_WIDTH bound to: 8 - type: integer
        Parameter SCM_DATA_WIDTH bound to: 128 - type: integer
        Parameter SET_ID_LSB bound to: 4 - type: integer
        Parameter SET_ID_MSB bound to: 7 - type: integer
        Parameter TAG_LSB bound to: 8 - type: integer
        Parameter TAG_MSB bound to: 14 - type: integer
        Parameter AXI_ID bound to: 6 - type: integer
        Parameter AXI_ADDR bound to: 32 - type: integer
        Parameter AXI_USER bound to: 6 - type: integer
        Parameter AXI_DATA bound to: 64 - type: integer
        Parameter OFFSET bound to: 4 - type: integer
ERROR: [Synth 8-523] part-select [3:4] does not match declaration [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/icache_mp_128_pf/RTL/icache_bank_mp_128.sv:253]
ERROR: [Synth 8-285] failed synthesizing module 'icache_bank_mp_128' [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/icache_mp_128_pf/RTL/icache_bank_mp_128.sv:48]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/icache_mp_128_pf/RTL/icache_top_mp_128_PF.sv:339]
ERROR: [Synth 8-285] failed synthesizing module 'icache_top_mp_128_PF' [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/icache_mp_128_pf/RTL/icache_top_mp_128_PF.sv:47]
ERROR: [Synth 8-285] failed synthesizing module 'pulp_cluster' [/local/speed/luebeck/git/pulp-platform/bigpulp/fe/ips/pulp_cluster/rtl/pulp_cluster.sv:24]

Do I have to adjust more values to synthesize for the ZedBoard?

Best regards

[andreaskurth]

Hi Konstantin,

Thank you for your report. The ZedBoard is not officially supported at the moment. If you have access to a ZC706 board, I suggest to use that board.

If you want to use the ZedBoard, you might encounter a few problems like the one you mentioned, so please be prepared to invest some time into them. We are willing to support the ZedBoard again, but we would require some help from you as we currently only have limited use for the ZedBoard ourselves. We had the configuration for the ZedBoard running about 1.5 years ago, but since then a couple of hardware components (e.g., the instruction cache in your log) have changed. Thus, I think the effort for getting bigPULP to run on the ZedBoard is not high, but it will require some debugging.

If you are willing to continue, I have created the branch zedboard where the problem with the I$ should be fixed. With that, the PULP cluster synthesizes fine for me, but I did not check functional correctness. Please switch to the zedboard branch, update the IPs, and try again to generate a bitstream.

The other problem regarding Synopsys DesignWare components should be fixed with the merge of #5, i.e., both on the current master and on zedboard.

Best,
Andreas

[k0nze]

Hi Andreas,

I actually tried building bigpulp for the ZedBoard since it was the only board available to me and on the list over here: https://pulp-platform.org/hero/doc/hardware/bigpulp/bitgen/ I actually would like to use bigpulp on the UltraScale+ MPSoC ZU3EG (UltraZed EG) or ZU9EG (ZCU102). And I'm not sure if the bigpulp-zux supports those boards.

Thanks for opening the zedboard branch I will have a look at it and might try bringing it onto the board.

Best regards,
Konstantin

[andreaskurth]

bigpulp-zux was developed on the ZU9EG, and the state of the hardware configuration is comparable to that of the ZedBoard: the configuration is pre-release and not officially supported at the moment. If you plan to use bigPULP together with the HERO SDK, you are better off with the ZedBoard, though, since 64-bit ARM hosts are currently not supported by the heterogeneous toolchain. If you want to use it standalone (i.e., with non-heterogeneous applications), I can offer you the same collaboration as with the ZedBoard.

Regarding the ZedBoard, I have fixed three more problems. At this point, top-level synthesis succeeds and implementation is currently ongoing.