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jmalmarijmalmari
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Add support for STM32H7 in gdbtrace.init
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‎Support/gdbtrace.init‎

Lines changed: 136 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ end
8181

8282
# Definitions for the CPU types we currently support
8383
set $CPU_IMXRT102X=1
84-
set $CPU_STM32=2
84+
set $CPU_STM32F1F4F7=2
8585
set $CPU_IMXRT106X=1
8686
set $CPU_NRF=3
8787
set $CPU_EFR32=4
@@ -91,6 +91,7 @@ set $CPU_IMXRT117X=7
9191
set $CPU_KINETIS=8
9292
set $CPU_SAMD5x=9
9393
set $CPU_STM32M33=10
94+
set $CPU_STM32H7=11
9495

9596
# ====================================================================
9697
set $CDBBASE=0xE000EDF0
@@ -113,14 +114,47 @@ end
113114

114115
define _setAddressesSTM32
115116
# Locations in the memory map for interesting things on STM32
116-
if ($CPU == $CPU_STM32M33)
117-
set $RCCBASE = 0x46020c00
118-
set $GPIOBASE = 0x42020000
119-
set $DBGMCUBASE = 0xE0044000
117+
118+
set $dev = $arg0
119+
120+
if ! $dev
121+
# Device type not specified, detect from DBGMCU ID register.
122+
if (*0x5C001000 & 0x7ff) == 0x450
123+
set $CPU = $CPU_STM32H7
124+
else
125+
set $CPU = $CPU_STM32F1F4F7
126+
end
120127
else
121-
set $RCCBASE = 0x40023800
122-
set $GPIOBASE = 0x40020000
123-
set $DBGMCUBASE = 0xE0042000
128+
if $dev == 33
129+
set $CPU = $CPU_STM32M33
130+
end
131+
if ($dev == 1) || ($dev == 4) || ($dev == 7)
132+
set $CPU = $CPU_STM32F1F4F7
133+
end
134+
end
135+
136+
if $CPU == $CPU_STM32M33
137+
set $GPIOBASE = 0x42020000
138+
set $RCCGPIO = 0x46020c8c
139+
set $DBGMCU_CR = 0xE0044004
140+
end
141+
142+
if $CPU == $CPU_STM32H7
143+
set $GPIOBASE = 0x58020000
144+
set $RCCGPIO = 0x580244E0
145+
set $DBGMCU_CR = 0x5C001004
146+
set $SWOBASE = 0x5C003000
147+
set $SWTFBASE = 0x5C004000
148+
set $CSTFBASE = 0x5C013000
149+
set $ETFBASE = 0x5C014000
150+
set $TPIUBASE = 0x5C015000
151+
end
152+
153+
if $CPU == $CPU_STM32F1F4F7
154+
set $GPIOBASE = 0x40020000
155+
set $RCCGPIO = 0x40023830
156+
set $DBGMCU_CR = 0xE0042004
157+
end
124158
end
125159

126160
define _setAddressesIMXRT
@@ -605,27 +639,37 @@ define prepareSWO
605639
unlockComponent $ITMBASE
606640
unlockComponent $DWTBASE
607641

642+
set $_formatterPresent=1
643+
set $_protocolBase=$TPIUBASE
644+
if $CPU == $CPU_STM32H7
645+
set $_formatterPresent=0
646+
set $_protocolBase=$SWOBASE
647+
unlockComponent $SWOBASE
648+
end
649+
608650
setTRCENA
609651

610652
if ($useMan==0)
611653
# Use Async mode pin protocol (TPIU_SPPR)
612-
set *($TPIUBASE+0xF0) = 2
654+
set *($_protocolBase+0xF0) = 2
613655
else
614656
# Use Manchester mode pin protocol (TPIU_SPPR)
615-
set *($TPIUBASE+0xF0) = 1
657+
set *($_protocolBase+0xF0) = 1
616658

617659
# There are two edges in a bit, so double the clock
618660
set $speed = $speed*2
619661
end
620662

621663
# Output bits at speed dependent on system clock
622-
set *($TPIUBASE+0x10) = ((($clockspeed+$speed-1)/$speed)-1)
664+
set *($_protocolBase+0x10) = ((($clockspeed+$speed-1)/$speed)-1)
623665

624-
if ($useTPIU==1)
625-
# Use TPIU formatter and flush
626-
set *($TPIUBASE+0x304) = 0x102
627-
else
628-
set *($TPIUBASE+0x304) = 0x100
666+
if $_formatterPresent==1
667+
if $useTPIU==1
668+
# Use TPIU formatter and flush
669+
set *($TPIUBASE+0x304) = 0x102
670+
else
671+
set *($TPIUBASE+0x304) = 0x100
672+
end
629673
end
630674

631675
# Flush all initial configuration
@@ -899,37 +943,47 @@ end
899943
define enableSTM32SWO
900944
#set language c
901945

902-
set $tgt=1
946+
set $dev=0
903947
if $argc >= 1
904-
set $tgt = $arg0
948+
set $dev = $arg0
905949
end
950+
_setAddressesSTM32 $dev
906951

907-
if ($tgt==33)
908-
set $CPU=$CPU_STM32M33
909-
else
910-
set $CPU=$CPU_STM32
952+
if $CPU == $CPU_STM32H7
953+
# Set D1DBGCKEN, D3DBGCKEN
954+
set *$DBGMCU_CR |= 7 | (6 << 20)
955+
# Unlock SWO trace funnel.
956+
unlockComponent $SWTFBASE
957+
# Enable port S0 in SWO trace funnel.
958+
set *($SWTFBASE + 0x000) = 0x00000301
959+
# SWO on PB3
960+
enableSTM32Pin 1 3 3
911961
end
912-
_setAddressesSTM32
913962

914-
if (($tgt==4) || ($tgt==7))
915-
# STM32F4/7 variant: SWO on PB3.
916-
enableSTM32Pin 1 3 3
917-
else
918-
# STM32F1 variant.
919-
# RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
920-
set *0x40021018 |= 1
921-
# AFIO->MAPR |= (2 << 24); // Disable JTAG to release TRACESWO
922-
set *0x40010004 |= 0x2000000
963+
if $CPU == $CPU_STM32F1F4F7
964+
if (($dev==4) || ($dev==7))
965+
# STM32F4/7 variant: SWO on PB3.
966+
enableSTM32Pin 1 3 3
967+
else
968+
# STM32F1 variant.
969+
# RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
970+
set *0x40021018 |= 1
971+
# AFIO->MAPR |= (2 << 24); // Disable JTAG to release TRACESWO
972+
set *0x40010004 |= 0x2000000
973+
end
974+
end
975+
976+
if $CPU != $CPU_STM32H7
977+
# Common initialisation.
978+
# DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN;
979+
set *$DBGMCU_CR |= 0x20
923980
end
924-
# Common initialisation.
925-
# DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN;
926-
set *($DBGMCUBASE+4) |= 0x20
927981

928982
#set language auto
929983
end
930984
document enableSTM32SWO
931985
enableSTM32SWO <Type> Configure output pin on STM32 for SWO use.
932-
<Type> : Type of STM32 Device 4=f4, 7=f7, 33=M33
986+
<Type> : Type of STM32 Device 1=f1, 4=f4, 7=f7, 33=M33
933987
end
934988
# ====================================================================
935989
define enableSAMD5XSWD
@@ -1030,15 +1084,11 @@ end
10301084
# ====================================================================
10311085
define enableSTM32Pin
10321086
#set language c
1033-
_setAddressesSTM32
1087+
10341088
set $_GPIOPORT = $GPIOBASE + 0x400 * $arg0
10351089

10361090
# Enable GPIO port in RCC
1037-
if ($CPU == $CPU_STM32M33)
1038-
set *($RCCBASE + 0x8c) |= (0x1<<$arg0)
1039-
else
1040-
set *($RCCBASE + 0x30) |= (0x1<<$arg0)
1041-
end
1091+
set *($RCCGPIO) |= (0x1<<$arg0)
10421092

10431093
# MODER: Alternate Function
10441094
set *($_GPIOPORT+0x00) &= ~(0x3<<2*$arg1)
@@ -1082,7 +1132,7 @@ define enableSTM32TRACE
10821132

10831133
set $bits=4
10841134
set $drive=1
1085-
set $type=1
1135+
set $dev=0
10861136

10871137
if $argc >= 1
10881138
set $bits = $arg0
@@ -1096,7 +1146,7 @@ define enableSTM32TRACE
10961146
end
10971147

10981148
if $argc >= 3
1099-
set $type = $arg2
1149+
set $dev = $arg2
11001150
end
11011151

11021152
if ($drive > 3)
@@ -1105,19 +1155,33 @@ define enableSTM32TRACE
11051155

11061156
set $bits = $bits-1
11071157

1108-
if ($type==33)
1109-
set $CPU=$CPU_STM32M33
1110-
else
1111-
set $CPU=$CPU_STM32
1112-
end
1113-
_setAddressesSTM32
1158+
_setAddressesSTM32 $dev
11141159

11151160
# Enable Trace TRCENA (DCB DEMCR) needed for clocks
11161161
setTRCENA
11171162

1118-
# Enable compensation cell
1119-
set *0x40023844 |= (1<<14)
1120-
set *0x40013820 |=1
1163+
if $CPU == $CPU_STM32H7
1164+
# Enable TRACECKEN, D1DBGCKEN
1165+
set *$DBGMCU_CR |= 7 | (3 << 20)
1166+
1167+
unlockComponent $ETFBASE
1168+
unlockComponent $CSTFBASE
1169+
unlockComponent $TPIUBASE
1170+
1171+
# Hardware FIFO mode
1172+
set *($ETFBASE + 0x028) = 2
1173+
# Formatter and flush control
1174+
set *($ETFBASE + 0x304) |= 1
1175+
# Enable ETF trace capture
1176+
set *($ETFBASE + 0x020) = 1
1177+
1178+
# Enable both ETM and ITM in trace funnel. bit0=ETM, bit1=ITM
1179+
set *($CSTFBASE + 0x000) |= 3
1180+
else
1181+
# Enable compensation cell
1182+
set *0x40023844 |= (1<<14)
1183+
set *0x40013820 |=1
1184+
end
11211185

11221186
# Setup PE2 & PE3
11231187
enableSTM32Pin 4 2 $drive
@@ -1134,17 +1198,29 @@ define enableSTM32TRACE
11341198
enableSTM32Pin 4 6 $drive
11351199
end
11361200

1137-
# Set number of bits in DBGMCU_CR
1138-
set *($DBGMCUBASE+4) &= ~(3<<6)
1201+
if $CPU != $CPU_STM32H7
1202+
# Set number of bits in DBGMCU_CR
1203+
set *$DBGMCU_CR &= ~(3<<6)
11391204

1140-
if ($bits<3)
1141-
set *($DBGMCUBASE+4) |= ((($bits+1)<<6) | (1<<5))
1142-
else
1143-
set *$(DBGMCUBASE+4) |= ((3<<6) | (1<<5))
1205+
if ($bits<3)
1206+
set *$DBGMCU_CR |= ((($bits+1)<<6) | (1<<5))
1207+
else
1208+
set *$DBGMCU_CR |= ((3<<6) | (1<<5))
1209+
end
11441210
end
11451211

11461212
# Finally start the trace output
1147-
_doTRACE
1213+
1214+
# Set port size (TPIU_CURPSIZE)
1215+
set *($TPIUBASE+4) = (1<<$bits)
1216+
1217+
if $CPU != $CPU_STM32H7
1218+
# Set pin protocol to Sync Trace Port (TPIU_SPPR)
1219+
set *($TPIUBASE+0xF0)=0
1220+
end
1221+
1222+
# TPIU formatter and flush control register (TPIU_FFCR)
1223+
set *($TPIUBASE+0x304) = 0x102
11481224

11491225
#set language auto
11501226
end

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