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Commit 85b66b9

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author
Dave Marples
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Simplify swd ack error handling
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verilog/swdIF.v

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -156,9 +156,9 @@ module swdIF (
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if (bitcount==PROT_ACK_END) // Have now done
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begin
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ack <= {swdi,rd[31:30]}; // Store the ACK
159-
if ({swdi,rd[31:30]}==3'b001) // Its a good one
159+
if ({swdi,rd[31:30]}!=3'b010) // Its not a wait
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begin
161-
if (rnw) // ..and we're reading
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if ((rnw) || ({swdi,rd[31:30]}!=3'b001)) // ..and we're reading or duff
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begin
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bitcount <= PROT_DATA;
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swd_state <= ST_DATA;
@@ -167,14 +167,14 @@ module swdIF (
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begin
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spincount <= turnaround; // Otherwise, its write
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swd_state <= ST_TRN2; // ..so turn again
170-
end // else: !if(rnw)
170+
end // else: !if((rnw) || ({swdi,rd[31:30]}!=3'b001))
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end
172-
else // Wasn't good, give up and return idle, via cooloff
172+
else // Was a wait, give up and return idle, via cooloff
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begin
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bitcount <= PROT_EOF;
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spincount <= dataphase?34:2; // Extended cool?
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swd_state <= ST_COOLING; // Go and cool off
177-
end // else: !if({swdi,rd[31:30]}==3'b001)
177+
end // else: !if({swdi,rd[31:30]}==3'b010)
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end // if (bitcount==PROT_ACK_END)
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end // case: ST_ACK
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