Skip to content

Commit 279b78e

Browse files
committed
trace.tpiu: Fix bug in packetizer.
1 parent b1edc6f commit 279b78e

File tree

2 files changed

+29
-4
lines changed

2 files changed

+29
-4
lines changed

orbtrace/trace/tpiu.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ def elaborate(self, platform):
182182
]
183183
m.next = 'END'
184184

185-
with m.If(self.input.valid & self.output.ready):
185+
with m.If(self.input.valid & self.input.ready):
186186
m.d.sync += [
187187
data.eq(self.input.payload.data),
188188
byte_cnt.eq(byte_cnt + 1),

tests/test_tpiu.py

Lines changed: 28 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,35 @@
22

33
from amaranth.sim import Simulator, SimulatorContext
44

5-
from orbtrace.trace.tpiu import TPIUDemux
5+
from orbtrace.trace import tpiu
66

7-
def test_serializer():
8-
dut = TPIUDemux(timeout = 1000)
7+
def test_packetizer():
8+
dut = tpiu.Packetizer(timeout = 1000)
9+
10+
sim = Simulator(dut)
11+
sim.add_clock(1e-6)
12+
13+
@sim.add_testbench
14+
async def input_testbench(ctx: SimulatorContext):
15+
await ctx.tick()
16+
17+
for i in range(1024 + 512):
18+
await stream_put(ctx, dut.input, {'channel': 1, 'data': i & 0xff})
19+
20+
@sim.add_testbench
21+
async def output_testbench(ctx: SimulatorContext):
22+
assert await recv_packet(ctx, dut.output) == [1, *((i & 0xff) for i in range(1024))]
23+
assert await recv_packet(ctx, dut.output) == [1, *((i & 0xff) for i in range(512))]
24+
25+
@sim.add_process
26+
async def timeout(ctx: SimulatorContext):
27+
await ctx.tick().repeat(10_000)
28+
raise TimeoutError('Simulation timed out')
29+
30+
sim.run()
31+
32+
def test_demux():
33+
dut = tpiu.TPIUDemux(timeout = 1000)
934

1035
sim = Simulator(dut)
1136
sim.add_clock(1e-6)

0 commit comments

Comments
 (0)