Missing Quartus specific constraints and attributes for 2-FF synchronizer

[Paebbels]

According to the IP core description file these synchronizers are intended to be used with Quartus. Unfortunately, Quartus specific constraints and attributes are missing:

• 2 times PRESERVE
• ALTERA_ATTRIBUTE setting SYNCHRONIZER_IDENTIFICATION

[olofk]

Yes, the intention is to use them for all kind of FPGAs and hopefully just switch in the correct constraints depending on the tool.
Haven't thought of setting those attributes, but you are right. It should also likely use the async_reg property for vivado.

Do you know if these can be set from the SDC file, or if they have to be set directly in the source. I'm not sure how to do this in a good way in the source code. For VHDL you can just pass the attribute value as a generic, but for verilog I think you are forced to use `ifdef to do the equivalent thing. Any ideas?

[Paebbels]

The experience from Vivado + VHDL is that it ignores lot's of attributes even if they are specified in the user guides. It might be a problem of the clocking wizard, because it complains that async_reg was not applied und needs a new line in the XDC despite the fact that it was already applied via VHDL attributes.

To answer your question: Yes, Vivado supports most of the properties and attributes to be applied via:

• VHDL attribute
• Verilog (how do they call it?), and
• XDC setting.

PoC uses vendor dependent implementations, that are chosen with generate statements based on the matching configuration:

• Generic
• Xilinx
• Altera