Experience Solving Common Setup and Vivado Timing Issues

[Tanawin1701d]

I would like to share my issues and my solution for each problem

• part 0 environment preparation (create conda envionment)

  • problem --> ModuleNotFoundError: No module named 'notebook.extensions'
    • solution --> Edit environment.yml from “notebook” to “notebook<7”
  • problem --> In part7, for who using xilinx toolchain >= 2020.2, will not have vivado_hls
    • solution --> install HLS4ML from this pull request Vitis Accelerator IP Flow hls4ml#1134 instead (This will give you "vitisAcceleratorBackend")

• part 3 compression

  • problem --> ModuleNotFoundError: No module named 'tensorflow_model_optimization'
    • solution --> pip install -U tensorflow-model-optimization

• part 5 bdt

  • problem --> on pynq z2, the vivado say "can't replace all shape"
    • since the hls design set the target clock at 200 MHz, the vivado can't place all shape
    • solution --> set the hls4ml target clock to 50 MHz
    • using this code
      • pynq_model_cfg['ClockPeriod'] = 20 # set the clock period to 20ns
        • the code should be

pynq_model_cfg = conifer.backends.xilinxhls.auto_config()
pynq_model_cfg['OutputDir'] = 'model_5_pynq'  # choose a new project directory
pynq_model_cfg['ProjectName'] = 'conifer_jettag'
pynq_model_cfg['XilinxPart'] = 'xc7z020clg400-1'
pynq_model_cfg['ClockPeriod'] = 20  # set the clock period to 20ns
pynq_model_cfg['AcceleratorConfig'] = {
    'Board': 'pynq-z2',  # choose a pynq-z2 board
    'InterfaceType': 'float',  # floating point for the data I/O (this is default)
}

# print the config
print('Modified Configuration\n' + '-' * 50)
print(json.dumps(pynq_model_cfg, indent=2))
print('-' * 50)

• part 7a
  • problem --> on vivado throw the critical warning "Timing constraints are not met"
    • solution ---> it "ultrascale plus block" -> "CLock Configuration" -> "Output Clocks" -> "Low Power Domain Clock" -> PL0 set to 50