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Merge: Rebase kernel's PCI subsystem with content from v6.16
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10/-/merge_requests/1484 ``` PCI updates from v6.16: "Enumeration: - Print the actual delay time in pci_bridge_wait_for_secondary_bus() instead of assuming it was 1000ms (Wilfred Mallawa) - Revert 'iommu/amd: Prevent binding other PCI drivers to IOMMU PCI devices', which broke resume from system sleep on AMD platforms and has been fixed by other commits (Lukas Wunner) Resource management: - Remove mtip32xx use of pcim_iounmap_regions(), which is deprecated and unnecessary (Philipp Stanner) - Remove pcim_iounmap_regions() and pcim_request_region_exclusive() and related flags since all uses have been removed (Philipp Stanner) - Rework devres 'request' functions so they are no longer 'hybrid', i.e., their behavior no longer depends on whether pcim_enable_device or pci_enable_device() was used, and remove related code (Philipp Stanner) - Warn (not BUG()) about failure to assign optional resources (Ilpo Järvinen) Error handling: - Log the DPC Error Source ID only when it's actually valid (when ERR_FATAL or ERR_NONFATAL was received from a downstream device) and decode into bus/device/function (Bjorn Helgaas) - Determine AER log level once and save it so all related messages use the same level (Karolina Stolarek) - Use KERN_WARNING, not KERN_ERR, when logging PCIe Correctable Errors (Karolina Stolarek) - Ratelimit PCIe Correctable and Non-Fatal error logging, with sysfs controls on interval and burst count, to avoid flooding logs and RCU stall warnings (Jon Pan-Doh) Power management: - Increment PM usage counter when probing reset methods so we don't try to read config space of a powered-off device (Alex Williamson) - Set all devices to D0 during enumeration to ensure ACPI opregion is connected via _REG (Mario Limonciello) Bandwidth control: - Simplify link bandwidth controller by replacing the count of Link Bandwidth Management Status (LBMS) events with a PCI_LINK_LBMS_SEEN flag (Ilpo Järvinen) - Update the Link Speed after retraining, since the Link Speed may have changed (Ilpo Järvinen) PCIe native device hotplug: - Ignore Presence Detect Changed caused by DPC. pciehp already ignores Link Down/Up events caused by DPC, but on slots using in-band presence detect, DPC causes a spurious Presence Detect Changed event (Lukas Wunner) - Ignore Link Down/Up caused by Secondary Bus Reset. On hotplug ports using in-band presence detect, the reset causes a Presence Detect Changed event, which mistakenly caused teardown and re-enumeration of the device. Drivers may need to annotate code that resets their device (Lukas Wunner) Virtualization: - Add an ACS quirk for Loongson Root Ports that don't advertise ACS but don't allow peer-to-peer transactions between Root Ports; the quirk allows each Root Port to be in a separate IOMMU group (Huacai Chen) Endpoint framework: - For fixed-size BARs, retain both the actual size and the possibly larger size allocated to accommodate iATU alignment requirements (Jerome Brunet) - Simplify ctrl/SPAD space allocation and avoid allocating more space than needed (Jerome Brunet) - Correct MSI-X PBA offset calculations for DesignWare and Cadence endpoint controllers (Niklas Cassel) - Align the return value (number of interrupts) encoding for pci_epc_get_msi()/pci_epc_ops::get_msi() and pci_epc_get_msix()/pci_epc_ops::get_msix() (Niklas Cassel) - Align the nr_irqs parameter encoding for pci_epc_set_msi()/pci_epc_ops::set_msi() and pci_epc_set_msix()/pci_epc_ops::set_msix() (Niklas Cassel) Common host controller library: - Convert pci-host-common to a library so platforms that don't need native host controller drivers don't need to include these helper functions (Manivannan Sadhasivam) Apple PCIe controller driver: - Extract ECAM bridge creation helper from pci_host_common_probe() to separate driver-specific things like MSI from PCI things (Marc Zyngier) - Dynamically allocate RID-to_SID bitmap to prepare for SoCs with varying capabilities (Marc Zyngier) - Skip ports disabled in DT when setting up ports (Janne Grunau) - Add t6020 compatible string (Alyssa Rosenzweig) - Add T602x PCIe support (Hector Martin) - Directly set/clear INTx mask bits because T602x dropped the accessors that could do this without locking (Marc Zyngier) - Move port PHY registers to their own reg items to accommodate T602x, which moves them around; retain default offsets for existing DTs that lack phy%d entries with the reg offsets (Hector Martin) - Stop polling for core refclk, which doesn't work on T602x and the bootloader has already done anyway (Hector Martin) - Use gpiod_set_value_cansleep() when asserting PERST# in probe because we're allowed to sleep there (Hector Martin) Cadence PCIe controller driver: - Drop a runtime PM 'put' to resolve a runtime atomic count underflow (Hans Zhang) - Make the cadence core buildable as a module (Kishon Vijay Abraham I) - Add cdns_pcie_host_disable() and cdns_pcie_ep_disable() for use by loadable drivers when they are removed (Siddharth Vadapalli) Freescale i.MX6 PCIe controller driver: - Apply link training workaround only on IMX6Q, IMX6SX, IMX6SP (Richard Zhu) - Remove redundant dw_pcie_wait_for_link() from imx_pcie_start_link(); since the DWC core does this, imx6 only needs it when retraining for a faster link speed (Richard Zhu) - Toggle i.MX95 core reset to align with PHY powerup (Richard Zhu) - Set SYS_AUX_PWR_DET to work around i.MX95 ERR051624 erratum: in some cases, the controller can't exit 'L23 Ready' through Beacon or PERST# deassertion (Richard Zhu) - Clear GEN3_ZRXDC_NONCOMPL to work around i.MX95 ERR051586 erratum: controller can't meet 2.5 GT/s ZRX-DC timing when operating at 8 GT/s, causing timeouts in L1 (Richard Zhu) - Wait for i.MX95 PLL lock before enabling controller (Richard Zhu) - Save/restore i.MX95 LUT for suspend/resume (Richard Zhu) Mobiveil PCIe controller driver: - Return bool (not int) for link-up check in mobiveil_pab_ops.link_up() and layerscape-gen4, mobiveil (Hans Zhang) NVIDIA Tegra194 PCIe controller driver: - Create debugfs directory for 'aspm_state_cnt' only when CONFIG_PCIEASPM is enabled, since there are no other entries (Hans Zhang) Qualcomm PCIe controller driver: - Add OF support for parsing DT 'eq-presets-<N>gts' property for lane equalization presets (Krishna Chaitanya Chundru) - Read Maximum Link Width from the Link Capabilities register if DT lacks 'num-lanes' property (Krishna Chaitanya Chundru) - Add Physical Layer 64 GT/s Capability ID and register offsets for 8, 32, and 64 GT/s lane equalization registers (Krishna Chaitanya Chundru) - Add generic dwc support for configuring lane equalization presets (Krishna Chaitanya Chundru) - Add DT and driver support for PCIe on IPQ5018 SoC (Nitheesh Sekar) Renesas R-Car PCIe controller driver: - Describe endpoint BAR 4 as being fixed size (Jerome Brunet) - Document how to obtain R-Car V4H (r8a779g0) controller firmware (Yoshihiro Shimoda) Rockchip PCIe controller driver: - Reorder rockchip_pci_core_rsts because reset_control_bulk_deassert() deasserts in reverse order, to fix a link training regression (Jensen Huang) - Mark RK3399 as being capable of raising INTx interrupts (Niklas Cassel) Rockchip DesignWare PCIe controller driver: - Check only PCIE_LINKUP, not LTSSM status, to determine whether the link is up (Shawn Lin) - Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s for Root Complex and Endpoint modes (Shawn Lin) - Hide the broken ATS Capability in rockchip_pcie_ep_init() instead of rockchip_pcie_ep_pre_init() so it stays hidden after PERST# resets non-sticky registers (Shawn Lin) - Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit() (Diederik de Haas) Synopsys DesignWare PCIe controller driver: - Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training more robust; this will not affect the intended link width if all lanes are functional (Wenbin Yao) - Return bool (not int) for link-up check in dw_pcie_ops.link_up() and armada8k, dra7xx, dw-rockchip, exynos, histb, keembay, keystone, kirin, meson, qcom, qcom-ep, rcar_gen4, spear13xx, tegra194, uniphier, visconti (Hans Zhang) TI J721E PCIe driver: - Make j721e buildable as a loadable and removable module (Siddharth Vadapalli) - Fix j721e host/endpoint dependencies that result in link failures in some configs (Arnd Bergmann) Device tree bindings: - Add qcom DT binding for 'global' interrupt (PCIe controller and link-specific events) for ipq8074, ipq8074-gen3, ipq6018, sa8775p, sc7280, sc8180x sdm845, sm8150, sm8250, sm8350 (Manivannan Sadhasivam) - Add qcom DT binding for 8 MSI SPI interrupts for msm8998, ipq8074, ipq8074-gen3, ipq6018 (Manivannan Sadhasivam) - Add dw rockchip DT binding for rk3576 and rk3562 (Kever Yang) - Correct indentation and style of examples in brcm,stb-pcie, cdns,cdns-pcie-ep, intel,keembay-pcie-ep, intel,keembay-pcie, microchip,pcie-host, rcar-pci-ep, rcar-pci-host, xilinx-versal-cpm (Krzysztof Kozlowski) - Convert Marvell EBU (dove, kirkwood, armada-370, armada-xp) and armada8k from text to schema DT bindings (Rob Herring) - Remove obsolete .txt DT bindings for content that has been moved to schemas (Rob Herring) - Add qcom DT binding for MHI registers in IPQ5332, IPQ6018, IPQ8074 and IPQ9574 (Varadarajan Narayanan) - Convert v3,v360epc-pci from text to DT schema binding (Rob Herring) - Change microchip,pcie-host DT binding to be 'dma-noncoherent' since PolarFire may be configured that way (Conor Dooley) Miscellaneous: - Drop 'pci' suffix from intel_mid_pci.c filename to match similar files (Andy Shevchenko) - All platforms with PCI have an MMU, so add PCI Kconfig dependency on MMU to simplify build testing and avoid inadvertent build regressions (Arnd Bergmann) - Update Krzysztof Wilczyński's email address in MAINTAINERS (Krzysztof Wilczyński) - Update Manivannan Sadhasivam's email address in MAINTAINERS (Manivannan Sadhasivam)" JIRA: https://issues.redhat.com/browse/RHEL-107597 Signed-off-by: Myron Stowe <mstowe@redhat.com> ``` Approved-by: John W. Linville <linville@redhat.com> Approved-by: Jerry Snitselaar <jsnitsel@redhat.com> Approved-by: Anusha Srivatsa <asrivats@redhat.com> Approved-by: David Airlie <airlied@redhat.com> Approved-by: Mika Penttilä <mpenttil@redhat.com> Approved-by: Enric Balletbo i Serra <eballetbo@redhat.com> Approved-by: Steve Best <sbest@redhat.com> Approved-by: Michal Schmidt <mschmidt@redhat.com> Approved-by: Ivan Vecera <ivecera@redhat.com> Approved-by: Lenny Szubowicz <lszubowi@redhat.com> Approved-by: Eric Chanudet <echanude@redhat.com> Approved-by: CKI KWF Bot <cki-ci-bot+kwf-gitlab-com@redhat.com> Merged-by: Scott Weaver <scweaver@redhat.com>
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‎.mailmap‎

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@@ -381,6 +381,8 @@ Krishna Manikandan <quic_mkrishn@quicinc.com> <mkrishn@codeaurora.org>
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Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
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Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
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Krzysztof Kozlowski <krzk@kernel.org> <krzysztof.kozlowski@canonical.com>
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Krzysztof Wilczyński <kwilczynski@kernel.org> <krzysztof.wilczynski@linux.com>
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Krzysztof Wilczyński <kwilczynski@kernel.org> <kw@linux.com>
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Kshitiz Godara <quic_kgodara@quicinc.com> <kgodara@codeaurora.org>
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Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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Kuogee Hsieh <quic_khsieh@quicinc.com> <khsieh@codeaurora.org>
@@ -418,6 +420,7 @@ Maheshwar Ajja <quic_majja@quicinc.com> <majja@codeaurora.org>
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Malathi Gottam <quic_mgottam@quicinc.com> <mgottam@codeaurora.org>
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Manikanta Pubbisetty <quic_mpubbise@quicinc.com> <mpubbise@codeaurora.org>
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Manivannan Sadhasivam <mani@kernel.org> <manivannanece23@gmail.com>
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Manivannan Sadhasivam <mani@kernel.org> <manivannan.sadhasivam@linaro.org>
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Manoj Basapathi <quic_manojbm@quicinc.com> <manojbm@codeaurora.org>
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Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
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Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>

‎Documentation/ABI/testing/debugfs-pcie-ptm‎

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What: /sys/kernel/debug/pcie_ptm_*/local_clock
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM local clock in nanoseconds. Applicable for both Root
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Complex and Endpoint controllers.
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What: /sys/kernel/debug/pcie_ptm_*/master_clock
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM master clock in nanoseconds. Applicable only for
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Endpoint controllers.
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What: /sys/kernel/debug/pcie_ptm_*/t1
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM T1 timestamp in nanoseconds. Applicable only for
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Endpoint controllers.
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What: /sys/kernel/debug/pcie_ptm_*/t2
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM T2 timestamp in nanoseconds. Applicable only for
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Root Complex controllers.
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What: /sys/kernel/debug/pcie_ptm_*/t3
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM T3 timestamp in nanoseconds. Applicable only for
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Root Complex controllers.
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What: /sys/kernel/debug/pcie_ptm_*/t4
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RO) PTM T4 timestamp in nanoseconds. Applicable only for
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Endpoint controllers.
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What: /sys/kernel/debug/pcie_ptm_*/context_update
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RW) Control the PTM context update mode. Applicable only for
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Endpoint controllers.
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Following values are supported:
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* auto = PTM context auto update trigger for every 10ms
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* manual = PTM context manual update. Writing 'manual' to this
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file triggers PTM context update (default)
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What: /sys/kernel/debug/pcie_ptm_*/context_valid
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Date: May 2025
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Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Description:
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(RW) Control the PTM context validity (local clock timing).
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Applicable only for Root Complex controllers. PTM context is
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invalidated by hardware if the Root Complex enters low power
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mode or changes link frequency.
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Following values are supported:
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* 0 = PTM context invalid (default)
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* 1 = PTM context valid

Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats renamed to Documentation/ABI/testing/sysfs-bus-pci-devices-aer

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KernelVersion: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: Total number of ERR_NONFATAL messages reported to rootport.
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PCIe AER ratelimits
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-------------------
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These attributes show up under all the devices that are AER capable.
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They represent configurable ratelimits of logs per error type.
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See Documentation/PCI/pcieaer-howto.rst for more info on ratelimits.
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What: /sys/bus/pci/devices/<dev>/aer/correctable_ratelimit_interval_ms
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Date: May 2025
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KernelVersion: 6.16.0
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Contact: linux-pci@vger.kernel.org
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Description: Writing 0 disables AER correctable error log ratelimiting.
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Writing a positive value sets the ratelimit interval in ms.
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Default is DEFAULT_RATELIMIT_INTERVAL (5000 ms).
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What: /sys/bus/pci/devices/<dev>/aer/correctable_ratelimit_burst
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Date: May 2025
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KernelVersion: 6.16.0
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Contact: linux-pci@vger.kernel.org
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Description: Ratelimit burst for correctable error logs. Writing a value
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changes the number of errors (burst) allowed per interval
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before ratelimiting. Reading gets the current ratelimit
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burst. Default is DEFAULT_RATELIMIT_BURST (10).
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What: /sys/bus/pci/devices/<dev>/aer/nonfatal_ratelimit_interval_ms
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Date: May 2025
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KernelVersion: 6.16.0
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Contact: linux-pci@vger.kernel.org
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Description: Writing 0 disables AER non-fatal uncorrectable error log
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ratelimiting. Writing a positive value sets the ratelimit
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interval in ms. Default is DEFAULT_RATELIMIT_INTERVAL
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(5000 ms).
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What: /sys/bus/pci/devices/<dev>/aer/nonfatal_ratelimit_burst
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Date: May 2025
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KernelVersion: 6.16.0
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Contact: linux-pci@vger.kernel.org
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Description: Ratelimit burst for non-fatal uncorrectable error logs.
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Writing a value changes the number of errors (burst)
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allowed per interval before ratelimiting. Reading gets the
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current ratelimit burst. Default is DEFAULT_RATELIMIT_BURST
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(10).

‎Documentation/PCI/controller/index.rst‎

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.. SPDX-License-Identifier: GPL-2.0
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===========================================
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PCI Native Host Bridge and Endpoint Drivers
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===========================================
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.. toctree::
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:maxdepth: 2
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rcar-pcie-firmware

‎Documentation/PCI/controller/rcar-pcie-firmware.rst‎

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.. SPDX-License-Identifier: GPL-2.0
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=================================================
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Firmware of PCIe controller for Renesas R-Car V4H
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=================================================
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Renesas R-Car V4H (r8a779g0) has a PCIe controller, requiring a specific
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firmware download during startup.
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However, Renesas currently cannot distribute the firmware free of charge.
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The firmware file "104_PCIe_fw_addr_data_ver1.05.txt" (note that the file name
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might be different between different datasheet revisions) can be found in the
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datasheet encoded as text, and as such, the file's content must be converted
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back to binary form. This can be achieved using the following example script:
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.. code-block:: sh
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$ awk '/^\s*0x[0-9A-Fa-f]{4}\s+0x[0-9A-Fa-f]{4}/ { print substr($2,5,2) substr($2,3,2) }' \
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104_PCIe_fw_addr_data_ver1.05.txt | \
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xxd -p -r > rcar_gen4_pcie.bin
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Once the text content has been converted into a binary firmware file, verify
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its checksum as follows:
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.. code-block:: sh
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$ sha1sum rcar_gen4_pcie.bin
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1d0bd4b189b4eb009f5d564b1f93a79112994945 rcar_gen4_pcie.bin
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The resulting binary file called "rcar_gen4_pcie.bin" should be placed in the
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"/lib/firmware" directory before the driver runs.

‎Documentation/PCI/index.rst‎

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pci-error-recovery
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pcieaer-howto
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endpoint/index
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controller/index
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boot-interrupts
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tph

‎Documentation/PCI/pcieaer-howto.rst‎

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the error message to the Root Port. Please refer to PCIe specs for other
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fields.
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AER Ratelimits
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--------------
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Since error messages can be generated for each transaction, we may see
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large volumes of errors reported. To prevent spammy devices from flooding
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the console/stalling execution, messages are throttled by device and error
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type (correctable vs. non-fatal uncorrectable). Fatal errors, including
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DPC errors, are not ratelimited.
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AER uses the default ratelimit of DEFAULT_RATELIMIT_BURST (10 events) over
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DEFAULT_RATELIMIT_INTERVAL (5 seconds).
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Ratelimits are exposed in the form of sysfs attributes and configurable.
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See Documentation/ABI/testing/sysfs-bus-pci-devices-aer.
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AER Statistics / Counters
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-------------------------
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When PCIe AER errors are captured, the counters / statistics are also exposed
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in the form of sysfs attributes which are documented at
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Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
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Documentation/ABI/testing/sysfs-bus-pci-devices-aer.
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Developer Guide
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===============

‎Documentation/devicetree/bindings/pci/apple,pcie.yaml‎

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implements its root ports. But the ATU found on most DesignWare
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PCIe host bridges is absent.
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On systems derived from T602x, the PHY registers are in a region
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separate from the port registers. In that case, there is one PHY
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register range per port register range.
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All root ports share a single ECAM space, but separate GPIOs are
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properties:
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compatible:
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items:
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- enum:
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- apple,t8103-pcie
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- apple,t8112-pcie
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- apple,t6000-pcie
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- const: apple,pcie
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oneOf:
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- items:
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- enum:
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- apple,t8103-pcie
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- apple,t8112-pcie
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- apple,t6000-pcie
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- const: apple,pcie
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- const: apple,t6020-pcie
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reg:
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maxItems: 6
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maxItems: 10
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reg-names:
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- const: port2
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- const: port3
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- const: phy0
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- const: phy1
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- const: phy2
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- const: phy3
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interrupts:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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const: apple,t6020-pcie
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then:
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properties:
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reg-names:
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minItems: 10
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examples:
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- |

‎Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml‎

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@@ -187,49 +187,48 @@ examples:
187187
#include <dt-bindings/interrupt-controller/arm-gic.h>
188188
189189
scb {
190-
#address-cells = <2>;
191-
#size-cells = <1>;
192-
pcie0: pcie@7d500000 {
193-
compatible = "brcm,bcm2711-pcie";
194-
reg = <0x0 0x7d500000 0x9310>;
195-
device_type = "pci";
196-
#address-cells = <3>;
197-
#size-cells = <2>;
198-
#interrupt-cells = <1>;
199-
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
200-
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
201-
interrupt-names = "pcie", "msi";
202-
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
203-
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
204-
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
205-
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
206-
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
207-
208-
msi-parent = <&pcie0>;
209-
msi-controller;
210-
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
211-
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
212-
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
213-
brcm,enable-ssc;
214-
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
215-
216-
/* PCIe bridge, Root Port */
217-
pci@0,0 {
218-
#address-cells = <3>;
219-
#size-cells = <2>;
220-
reg = <0x0 0x0 0x0 0x0 0x0>;
221-
compatible = "pciclass,0604";
222-
device_type = "pci";
223-
vpcie3v3-supply = <&vreg7>;
224-
ranges;
225-
226-
/* PCIe endpoint */
227-
pci-ep@0,0 {
228-
assigned-addresses =
229-
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
230-
reg = <0x0 0x0 0x0 0x0 0x0>;
231-
compatible = "pci14e4,1688";
232-
};
233-
};
190+
#address-cells = <2>;
191+
#size-cells = <1>;
192+
pcie0: pcie@7d500000 {
193+
compatible = "brcm,bcm2711-pcie";
194+
reg = <0x0 0x7d500000 0x9310>;
195+
device_type = "pci";
196+
#address-cells = <3>;
197+
#size-cells = <2>;
198+
#interrupt-cells = <1>;
199+
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
200+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
201+
interrupt-names = "pcie", "msi";
202+
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
203+
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
204+
0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
205+
0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
206+
0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
207+
208+
msi-parent = <&pcie0>;
209+
msi-controller;
210+
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
211+
dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
212+
<0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
213+
brcm,enable-ssc;
214+
brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
215+
216+
/* PCIe bridge, Root Port */
217+
pci@0,0 {
218+
#address-cells = <3>;
219+
#size-cells = <2>;
220+
reg = <0x0 0x0 0x0 0x0 0x0>;
221+
compatible = "pciclass,0604";
222+
device_type = "pci";
223+
vpcie3v3-supply = <&vreg7>;
224+
ranges;
225+
226+
/* PCIe endpoint */
227+
pci-ep@0,0 {
228+
assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
229+
reg = <0x0 0x0 0x0 0x0 0x0>;
230+
compatible = "pci14e4,1688";
231+
};
234232
};
233+
};
235234
};

‎Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,14 @@ examples:
3737
#size-cells = <2>;
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pcie-ep@fc000000 {
40-
compatible = "cdns,cdns-pcie-ep";
41-
reg = <0x0 0xfc000000 0x0 0x01000000>,
42-
<0x0 0x80000000 0x0 0x40000000>;
43-
reg-names = "reg", "mem";
44-
cdns,max-outbound-regions = <16>;
45-
max-functions = /bits/ 8 <8>;
46-
phys = <&pcie_phy0>;
47-
phy-names = "pcie-phy";
40+
compatible = "cdns,cdns-pcie-ep";
41+
reg = <0x0 0xfc000000 0x0 0x01000000>,
42+
<0x0 0x80000000 0x0 0x40000000>;
43+
reg-names = "reg", "mem";
44+
cdns,max-outbound-regions = <16>;
45+
max-functions = /bits/ 8 <8>;
46+
phys = <&pcie_phy0>;
47+
phy-names = "pcie-phy";
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};
4949
};
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...

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