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This repository was archived by the owner on Jun 26, 2020. It is now read-only.
This repository was archived by the owner on Jun 26, 2020. It is now read-only.

Using pinned base registers in Cranelift #1396

@shravanrn

Description

@shravanrn

Feature

I am a PhD student at UCSD investigating a variety of cranelift performance improvements and cranelift Spectre related hardening. So far, these appear very promising and I am hoping to contribute this back to cranelift in the future.

However a key requirement for this work is being able to pin the heap base register in the cranelift compiler. I believe there was support for this earlier, but the feature has since been removed. I am looking for a way to re-enable or re-implement this. I am using cranelift via the Lucet AOT wasm compiler.

Benefit

This will allow for analysis and prototyping of various performance improvements and Spectre related hardening for the cranelift compiler.

Implementation

I believe there was support for this earlier, but this was removed. I am looking for a way to re-enable or re-implement this. A quick and dirty hack for this is fine too, as this is for prototyping, and is not meant for production.

Alternatives

Unfortunately, all of the approaches I am investigating explicitly rely on pinned base registers.

@sunfishcode, @pchickey - We had spoken at the WASM CG about some of this. Would you have thoughts on how best I can proceed here?

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