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bsatrombsatrom
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Merge pull request #8 from m-mcgowan/fix/mat_cygnet
fix: USB CDC/MDC on Cygnet
2 parents 2f96fe7 + edb90a4 commit 70dc681

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6 files changed

+69
-54
lines changed

6 files changed

+69
-54
lines changed

‎ports/stm/boards/STM32L433_boot.ld‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ MEMORY
77
{
88
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* entire flash */
99
FLASH_ISR (rx) : ORIGIN = 0x08010000, LENGTH = 4K /* ISR vector. Kind of wasteful. */
10-
FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 192K-64K-4K /* For now, limit to 1MB so that bank switching is still possible. */
10+
FLASH_FIRMWARE (rx) : ORIGIN = 0x08011000, LENGTH = 192K-64K-4K
1111
FLASH_FS (rw) : ORIGIN = 0x08030000, LENGTH = 60K
1212
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
1313
}

‎ports/stm/common-hal/microcontroller/__init__.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -31,25 +31,25 @@ void common_hal_mcu_delay_us(uint32_t delay) {
3131
SysTick->CTRL = 0UL;
3232
}
3333

34-
volatile uint32_t nesting_count = 0;
34+
static volatile uint32_t nesting_count = 0;
3535

36+
// 32-bit increments
3637
void common_hal_mcu_disable_interrupts(void) {
37-
__disable_irq();
38-
__DMB();
39-
nesting_count++;
38+
if (++nesting_count==1) {
39+
__disable_irq();
40+
__DMB();
41+
}
4042
}
4143

4244
void common_hal_mcu_enable_interrupts(void) {
4345
if (nesting_count == 0) {
4446
// This is very very bad because it means there was mismatched disable/enables.
4547
reset_into_safe_mode(SAFE_MODE_INTERRUPT_ERROR);
4648
}
47-
nesting_count--;
48-
if (nesting_count > 0) {
49-
return;
49+
if (--nesting_count == 0) {
50+
__DMB();
51+
__enable_irq();
5052
}
51-
__DMB();
52-
__enable_irq();
5353
}
5454

5555
static bool next_reset_to_bootloader = false;

‎ports/stm/peripherals/periph.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,3 +137,7 @@ typedef struct {
137137
#define HAS_BASIC_TIM 0
138138
#include "stm32h7/stm32h743xx/periph.h"
139139
#endif
140+
141+
#if !defined(HAS_DAC)
142+
#error Unknown MCU
143+
#endif

‎ports/stm/peripherals/stm32l4/clocks.c‎

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@
99
#include <stdbool.h>
1010

1111
// L4 Series
12-
#ifdef STM32L4R5xx
12+
#if defined(STM32L4R5xx)
1313
#include "stm32l4/stm32l4r5xx/clocks.h"
14-
#elif STM32L433xx
14+
#elif defined(STM32L433xx)
1515
#include "stm32l4/stm32l433xx/clocks.h"
1616
#else
1717
#error Please add other MCUs here so that they are not silently ignored due to #define typos
@@ -46,18 +46,18 @@ void stm32_peripherals_clocks_init(void) {
4646

4747
/** Configure the main internal regulator output voltage
4848
*/
49-
#if STM32L4R5xx
49+
#if defined(STM32L4R5xx)
5050
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK) {
5151
Error_Handler();
5252
}
53-
#elif STM32L433xx
53+
#elif defined(STM32L433xx)
5454
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
5555
Error_Handler();
5656
}
5757
#endif
5858

5959
/* Activate PLL with MSI , stabilizied via PLL by LSE */
60-
#ifdef STM32L4R5xx
60+
#if defined(STM32L4R5xx)
6161
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
6262
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
6363
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -70,7 +70,7 @@ void stm32_peripherals_clocks_init(void) {
7070
RCC_OscInitStruct.PLL.PLLN = 30;
7171
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
7272
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
73-
#elif STM32L433xx
73+
#elif defined(STM32L433xx)
7474
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI;
7575
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
7676
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -84,6 +84,8 @@ void stm32_peripherals_clocks_init(void) {
8484
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
8585
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8686
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
87+
#else
88+
#error Unknown MCU
8789
#endif
8890

8991
HAL_CHECK(HAL_RCC_OscConfig(&RCC_OscInitStruct));
@@ -100,10 +102,12 @@ void stm32_peripherals_clocks_init(void) {
100102
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
101103
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
102104
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
103-
#ifdef STM32L4R5xx
105+
#if defined(STM32L4R5xx)
104106
HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3));
105-
#elif STM32L433xx
107+
#elif defined(STM32L433xx)
106108
HAL_CHECK(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4));
109+
#else
110+
#error Please expand the conditional compilation to set the default flash latency
107111
#endif
108112

109113
/* AHB prescaler divider at 1 as second step */
@@ -115,9 +119,9 @@ void stm32_peripherals_clocks_init(void) {
115119

116120
/* Select MSI output as USB clock source */
117121
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ADC;
118-
#ifdef STM32L4R5xx
122+
#if defined(STM32L4R5xx)
119123
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
120-
#elif STM32L433xx
124+
#elif defined(STM32L433xx)
121125
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
122126
#endif
123127
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;

‎ports/stm/supervisor/internal_flash.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,13 +69,13 @@ static const flash_layout_t flash_layout[] = {
6969
};
7070
static uint8_t _flash_cache[0x20000] __attribute__((aligned(4)));
7171

72-
#elif defined(STM32L4R5XX)
72+
#elif defined(STM32L4R5xx)
7373
static const flash_layout_t flash_layout[] = {
7474
{ 0x08100000, 0x1000, 256 },
7575
};
7676
static uint8_t _flash_cache[0x1000] __attribute__((aligned(4)));
7777

78-
#elif defined(STM32L433XX)
78+
#elif defined(STM32L433xx)
7979
static const flash_layout_t flash_layout[] = {
8080
{ 0x08000000, 0x0800, 128 },
8181
};
@@ -181,10 +181,10 @@ void port_internal_flash_flush(void) {
181181
// set up for erase
182182
FLASH_EraseInitTypeDef EraseInitStruct = {};
183183
#if CPY_STM32L4
184-
#if defined(STM32L4R5XX)
184+
#if defined(STM32L4R5xx)
185185
EraseInitStruct.TypeErase = TYPEERASE_PAGES;
186186
EraseInitStruct.Banks = FLASH_BANK_2; // filesystem stored in upper 1MB of flash in dual bank mode
187-
#elif defined(STM32L433XX)
187+
#elif defined(STM32L433xx)
188188
EraseInitStruct.TypeErase = TYPEERASE_PAGES;
189189
EraseInitStruct.Banks = FLASH_BANK_1;
190190
#endif

‎ports/stm/supervisor/usb.c‎

Lines changed: 37 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -14,34 +14,33 @@
1414
#include "common-hal/microcontroller/Pin.h"
1515

1616
static void init_usb_vbus_sense(void) {
17-
1817
#if (BOARD_NO_VBUS_SENSE)
19-
// Disable VBUS sensing
20-
#ifdef USB_OTG_GCCFG_VBDEN
21-
// Deactivate VBUS Sensing B
22-
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
23-
24-
#if (BOARD_NO_USB_OTG_ID_SENSE)
25-
USB_OTG_FS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
26-
USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
27-
#endif
28-
29-
// B-peripheral session valid override enable
30-
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
31-
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
32-
#elif !defined(STM32L433XX)
33-
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
34-
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
35-
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
36-
#endif
18+
// Disable VBUS sensing
19+
#ifdef USB_OTG_GCCFG_VBDEN
20+
// Deactivate VBUS Sensing B
21+
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
22+
23+
#if (BOARD_NO_USB_OTG_ID_SENSE)
24+
USB_OTG_FS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
25+
USB_OTG_FS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
26+
#endif // BOARD_NO_USB_OTG_ID_SENSE
27+
28+
// B-peripheral session valid override enable
29+
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
30+
USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
31+
32+
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
33+
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
34+
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
35+
#endif
3736
#else
38-
// Enable VBUS hardware sensing
39-
#ifdef USB_OTG_GCCFG_VBDEN
40-
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
41-
#else
42-
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
43-
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense
44-
#endif
37+
// Enable VBUS hardware sensing
38+
#ifdef USB_OTG_GCCFG_VBDEN
39+
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
40+
#else
41+
USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
42+
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; // B Device sense
43+
#endif
4544
#endif
4645
}
4746

@@ -69,12 +68,15 @@ void init_usb_hardware(void) {
6968
GPIO_InitStruct.Pull = GPIO_NOPULL;
7069
#if CPY_STM32H7
7170
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
72-
#elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX)
71+
#elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx)
7372
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
74-
#elif defined(STM32L433XX)
73+
#elif defined(STM32L433xx)
7574
GPIO_InitStruct.Alternate = GPIO_AF10_USB_FS;
75+
#else
76+
#error Unknown MCU
7677
#endif
7778
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
79+
7880
never_reset_pin_number(0, 11);
7981
never_reset_pin_number(0, 12);
8082
claim_pin(0, 11);
@@ -119,7 +121,7 @@ void init_usb_hardware(void) {
119121
#if CPY_STM32H7
120122
HAL_PWREx_EnableUSBVoltageDetector();
121123
__HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
122-
#elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5XX)
124+
#elif CPY_STM32F4 || CPY_STM32F7 || defined(STM32L4R5xx)
123125
/* Peripheral clock enable */
124126
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
125127
#else
@@ -129,6 +131,11 @@ void init_usb_hardware(void) {
129131
init_usb_vbus_sense();
130132
}
131133

132-
void OTG_FS_IRQHandler(void) {
134+
#if defined(STM32L433xx)
135+
void USB_IRQHandler(void)
136+
#else
137+
void OTG_FS_IRQHandler(void)
138+
#endif
139+
{
133140
usb_irq_handler(0);
134141
}

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