Greetings, It is not necesseraly an issue that i have more of general questions about using vunit as a runner for system level VHDL verification environment; can it be used to verify multiple vhdl designs with vivado ip's in a way such that the projects use different versions of vivado for 2 different fpga's connected to each other, since they are both trying to acces the same library such as secure ip and xpm and unisim etc but they are from different versions will it cause a problem, My second question is more on the same spirit can it be used in a way some of the ips on the design is from one version whereas rest of the design is from another version. for example the x ip is from 2023.2 but rest of the design is from 2020.2.
Greetings, It is not necesseraly an issue that i have more of general questions about using vunit as a runner for system level VHDL verification environment; can it be used to verify multiple vhdl designs with vivado ip's in a way such that the projects use different versions of vivado for 2 different fpga's connected to each other, since they are both trying to acces the same library such as secure ip and xpm and unisim etc but they are from different versions will it cause a problem, My second question is more on the same spirit can it be used in a way some of the ips on the design is from one version whereas rest of the design is from another version. for example the x ip is from 2023.2 but rest of the design is from 2020.2.