Design UART communication module

[TheDeepestSpace]

We need to somehow communicate with our core from the outside; UART seems like the most natural choice for a TTO design. We will need at least the following functionality:

• write data into the memory of the core
• read data from the the memory of the core
• gather metadata on the state of the core (this is tentative, but ideally we would want to be able to get some debugging info in case the cpu gets stuck or outputs incorrect data)

[TheDeepestSpace]

This has been prototyped for FPGA as part of UTOSS/risc-v#154; As per today's meeting we would like to consume the UART modules added as part of that PR in the top module of the ASIC design. I think the interface might change somewhat as we are finalizing the implementation in the main repo but I think the bulk of the structure will remain stable.

cc @marwannismail