-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathstateMachine.sv
More file actions
449 lines (437 loc) · 8.85 KB
/
stateMachine.sv
File metadata and controls
449 lines (437 loc) · 8.85 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
`define S0 5'b00000 //wait
`define S1 5'b00001 //Decode
`define S2 5'b00010 //MOV
`define S3 5'b00011 //ALU
`define S4 5'b00100 //MOV with constant
`define S5 5'b00101 //MOV with another register: load reg
`define S6 5'b00110 //MOV with another register: shift
`define S7 5'b00111 //MOV with another register: move into reg
`define S8 5'b01000 //ADD: GetA
`define S9 5'b01001 //ADD: GetB
`define S10 5'b01010 //ADD: Add
`define S11 5'b01011 //ADD: Store
`define S12 5'b01100 //CMP: GetA
`define S13 5'b01101 //CMP: GetB
`define S14 5'b01110 //CMP: Shift, subtract
`define S15 5'b01111 //AND: GetA
`define S16 5'b10000 //AND: GetB
`define S17 5'b10001 //AND: And
`define S18 5'b10010 //AND: Store
`define S19 5'b10011 //NOT: GetB
`define S20 5'b10100 //NOT: Not
`define S21 5'b10101 //NOT: Store
`define S22 5'b10110 //TEST
module stateMachine(in, s, clk, reset, loada, loadb, loadc, loads, shift, ALUop, asel, bsel, vsel, write, nsel, w, im8);
input s, clk, reset;
input [15:0] in;
wire [2:0] opcode = in[15:13];
wire [1:0] op = in[12:11];
output reg [2:0] nsel; // 001 Rn, 010 Rd, 100 Rm one hot encoding
output reg loada, loadb, loadc, loads, write, w, asel, bsel;
output reg [1:0] shift, ALUop, vsel;
output reg [7:0] im8;
reg [4:0] presentState;
always_ff @(posedge clk) begin
if(reset) begin
presentState <= `S0;
end
else begin
case(presentState)
`S0: presentState <= s ? `S1 : `S0;
`S1: begin
case(opcode)
3'b110: presentState <= `S2;
3'b101: presentState <= `S3;
default: presentState <= `S1;
endcase
end
`S2: begin
case(op)
2'b10: presentState <= `S4;
2'b00: presentState <= `S5;
default: presentState <= presentState;
endcase
end
`S3: begin
case(op)
2'b00: presentState <= `S8;
2'b01: presentState <= `S12;
2'b10: presentState <= `S15;
2'b11: presentState <= `S19;
endcase
end
`S4: presentState <= `S0;
`S5: presentState <= `S6;
`S6: presentState <= `S7;
`S7: presentState <= `S0;
`S8: presentState <= `S9;
`S9: presentState <= `S10;
`S10: presentState <= `S11;
`S11: presentState <= `S0;
`S12: presentState <= `S13;
`S13: presentState <= `S14;
`S14: presentState <= `S0;
`S15: presentState <= `S16;
`S16: presentState <= `S17;
`S17: presentState <= `S18;
`S18: presentState <= `S19;
`S19: presentState <= `S20;
`S20: presentState <= `S21;
`S21: presentState <= `S0;
default: presentState <= presentState;
endcase
end
end
always_comb begin
case(presentState) //TODO: Decide what to do with this
/* Since these first few don't do anything to the datapath,
send out null values. This will also help us catch inferred latches
*/
`S0: begin //Wait
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'bx;
loada = 1'b0;
loadb = 1'b0;
loadc = 1'b0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
w = 1'b1;
im8 = 8'bx;
end
`S1: begin //Decode
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'bx;
nsel = 3'bx;
loada = 1'b0;
loadb = 1'b0;
loadc = 1'b0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
w = 1'b0;
im8 = 8'bx;
end
`S2: begin //MOV
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'bx;
nsel = 3'bx;
loada = 1'b0;
loadb = 1'b0;
loadc = 1'b0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S3: begin //ALU
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'bx;
nsel = 3'bx;
loada = 1'b0;
loadb = 1'b0;
loadc = 1'b0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S4: begin //MOV with constant
vsel = 2'b01;
asel = 1'bx;
bsel = 1'bx;
write = 1'b1;
nsel = 3'b001;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = in[7:0];
w = 1'b0;
end
`S5: begin //Mov with another reg
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b100;
loada = 0;
loadb = 1;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S6: begin //MOV with another register: shift
vsel = 2'bxx;
asel = 1'b1;
bsel = 1'b0;
write = 1'b0;
nsel = 3'b000;
loada = 0;
loadb = 0;
loadc = 1;
loads = 1'b0;
ALUop = 2'b00;
shift = in[4:3];
im8 = 8'bx;
w = 1'b0;
end
`S7: begin //MOV with another register: move into reg
vsel = 2'b11;
asel = 1'bx;
bsel = 1'bx;
write = 1'b1;
nsel = 3'b010;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S8: begin //ADD: GetA
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b001;
loada = 1;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S9: begin //ADD: GetB
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b100;
loada = 0;
loadb = 1;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S10: begin //ADD: Add
vsel = 2'bxx;
asel = 1'b0;
bsel = 1'b0;
write = 1'b0;
nsel = 3'b000;
loada = 0;
loadb = 0;
loadc = 1;
loads = 1'b0;
ALUop = 2'b00;
shift = in[4:3];
im8 = 8'bx;
w = 1'b0;
end
`S11: begin //ADD: Store
vsel = 2'b11;
asel = 1'bx;
bsel = 1'bx;
write = 1'b1;
nsel = 3'b010;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'b00;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S12: begin //CMP: GetA
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b001;
loada = 1;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S13: begin //CMP: GetB
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b100;
loada = 0;
loadb = 1;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S14: begin //CMP: Shift, subtract
vsel = 2'bxx;
asel = 1'b0;
bsel = 1'b0;
write = 1'b0;
nsel = 3'b000;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b1;
ALUop = 2'b01;
shift = in[4:3];
im8 = 8'bx;
w = 1'b0;
end
`S15: begin //AND: GetA
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b001;
loada = 1;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S16: begin //AND: GetB
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'b100;
loada = 0;
loadb = 1;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S17: begin //AND: And
vsel = 2'bxx;
asel = 1'b0;
bsel = 1'b0;
write = 1'b0;
nsel = 3'b000;
loada = 0;
loadb = 0;
loadc = 1;
loads = 1'b0;
ALUop = 2'b10;
shift = in[4:3];
im8 = 8'bx;
w = 1'b0;
end
`S18: begin //AND: Store
vsel = 2'b11;
asel = 1'bx;
bsel = 1'bx;
write = 1'b1;
nsel = 3'b010;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'b00;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
`S19: begin //NOT: GetB
vsel = 2'bxx;
asel = 1'b0;
bsel = 1'b0;
write = 1'b1;
nsel = 3'b001;
loada = 0;
loadb = 1;
loadc = 0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'b0;
im8 = 8'bx;
w = 1'b0;
end
`S20: begin//NOT: Not
vsel = 2'bxx;
asel = 1'b1;
bsel = 1'b0;
write = 1'b0;
nsel = 3'b001;
loada = 0;
loadb = 0;
loadc = 1;
loads = 1'b0;
ALUop = 2'b11;
shift = in[4:3];
im8 = 8'bx;
w = 1'b0;
end
`S21: begin //NOT: Store
vsel = 2'b11;
asel = 1'bx;
bsel = 1'bx;
write = 1'b1;
nsel = 3'b010;
loada = 0;
loadb = 0;
loadc = 0;
loads = 1'b0;
ALUop = 2'b00;
shift = 2'bxx;
im8 = 8'bx;
w = 1'b0;
end
default: begin
vsel = 2'bxx;
asel = 1'bx;
bsel = 1'bx;
write = 1'b0;
nsel = 3'bx;
loada = 1'b0;
loadb = 1'b0;
loadc = 1'b0;
loads = 1'b0;
ALUop = 2'bxx;
shift = 2'bxx;
w = 1'b0;
im8 = 8'bx;
end
endcase
end
endmodule